#define SECOND_DEMUX_OFFSET_0  0x50
#define THIRD_DEMUX_OFFSET_0   0xa0
#define STB_TOP_CONFIG                             0x16f0
#define TS_TOP_CONFIG                              0x16f1
#define TS_FILE_CONFIG                             0x16f2
#define TS_PL_PID_INDEX                            0x16f3
#define TS_PL_PID_DATA                             0x16f4
#define COMM_DESC_KEY0                             0x16f5
#define COMM_DESC_KEY1                             0x16f6
#define COMM_DESC_KEY_RW                           0x16f7
#define PREG_CTLREG0_ADDR                          0x2000
#define PREG_PAD_GPIO6_EN_N                        0x2008
#define PREG_PAD_GPIO6_O                           0x2009
#define PREG_PAD_GPIO6_I                           0x200a
#define PREG_JTAG_GPIO_ADDR                        0x200b
#define PREG_PAD_GPIO0_EN_N                        0x200c
#define PREG_PAD_GPIO0_O                           0x200d
#define PREG_PAD_GPIO0_I                           0x200e
#define PREG_PAD_GPIO1_EN_N                        0x200f
#define PREG_PAD_GPIO1_O                           0x2010
#define PREG_PAD_GPIO1_I                           0x2011
#define PREG_PAD_GPIO2_EN_N                        0x2012
#define PREG_PAD_GPIO2_O                           0x2013
#define PREG_PAD_GPIO2_I                           0x2014
#define PREG_PAD_GPIO3_EN_N                        0x2015
#define PREG_PAD_GPIO3_O                           0x2016
#define PREG_PAD_GPIO3_I                           0x2017
#define PREG_PAD_GPIO4_EN_N                        0x2018
#define PREG_PAD_GPIO4_O                           0x2019
#define PREG_PAD_GPIO4_I                           0x201a
#define PREG_PAD_GPIO5_EN_N                        0x201b
#define PREG_PAD_GPIO5_O                           0x201c
#define PREG_PAD_GPIO5_I                           0x201d
#define A9_CFG0                                    0x2020
#define A9_CFG1                                    0x2021
#define A9_CFG2                                    0x2022
#define A9_PERIPH_BASE                             0x2023
#define A9_L2_REG_BASE                             0x2024
#define A9_L2_STATUS                               0x2025
#define A9_POR_CFG                                 0x2026
#define MALI_IDLE_STAT                             0x2027
#define AXI_REG_EN                                 0x2028
#define PERIPHS_PIN_MUX_0                          0x202c
#define PERIPHS_PIN_MUX_1                          0x202d
#define PERIPHS_PIN_MUX_2                          0x202e
#define PERIPHS_PIN_MUX_3                          0x202f
#define PERIPHS_PIN_MUX_4                          0x2030
#define PERIPHS_PIN_MUX_5                          0x2031
#define PERIPHS_PIN_MUX_6                          0x2032
#define PERIPHS_PIN_MUX_7                          0x2033
#define PERIPHS_PIN_MUX_8                          0x2034
#define PERIPHS_PIN_MUX_9                          0x2035
#define PERIPHS_PIN_MUX_10                         0x2036
#define PERIPHS_PIN_MUX_11                         0x2037
#define PERIPHS_PIN_MUX_12                         0x2038
#define PAD_PULL_UP_REG6                           0x2039
#define PAD_PULL_UP_REG0                           0x203a
#define PAD_PULL_UP_REG1                           0x203b
#define PAD_PULL_UP_REG2                           0x203c
#define PAD_PULL_UP_REG3                           0x203d
#define PAD_PULL_UP_REG4                           0x203e
#define PAD_PULL_UP_REG5                           0x203f
#define RAND64_ADDR0                               0x2040
#define RAND64_ADDR1                               0x2041
#define PREG_ETHERNET_ADDR0                        0x2042
#define PREG_AM_ANALOG_ADDR                        0x2043
#define PREG_MALI_BYTE_CNTL                        0x2044
#define PREG_WIFI_CNTL                             0x2045
#define AM_ANALOG_TOP_REG0                         0x206e
#define AM_ANALOG_TOP_REG1                         0x206f
#define PREG_STICKY_REG0                           0x207c
#define PREG_STICKY_REG1                           0x207d
#define PREG_MV_REG                                0x207e
#define AM_RING_OSC_REG0                           0x207f
#define USB_ADDR0                                  0x2100
#define USB_ADDR1                                  0x2101
#define USB_ADDR2                                  0x2102
#define USB_ADDR3                                  0x2103
#define USB_ADDR4                                  0x2104
#define USB_ADDR5                                  0x2105
#define USB_ADDR6                                  0x2106
#define USB_ADDR7                                  0x2107
#define USB_ADDR8                                  0x2108
#define USB_ADDR9                                  0x2109
#define USB_ADDR10                                 0x210a
#define USB_ADDR11                                 0x210b
#define USB_ADDR12                                 0x210c
#define USB_ADDR13                                 0x210d
#define USB_ADDR14                                 0x210e
#define USB_ADDR15                                 0x210f
#define SMARTCARD_REG0                             0x2110
#define SMARTCARD_REG1                             0x2111
#define SMARTCARD_REG2                             0x2112
#define SMARTCARD_STATUS                           0x2113
#define SMARTCARD_INTR                             0x2114
#define SMARTCARD_REG5                             0x2115
#define SMARTCARD_REG6                             0x2116
#define SMARTCARD_FIFO                             0x2117
#define IR_DEC_LDR_ACTIVE                          0x2120
#define IR_DEC_LDR_IDLE                            0x2121
#define IR_DEC_LDR_REPEAT                          0x2122
#define IR_DEC_BIT_0                               0x2123
#define IR_DEC_REG0                                0x2124
#define IR_DEC_FRAME                               0x2125
#define IR_DEC_STATUS                              0x2126
#define IR_DEC_REG1                                0x2127
#define DEMOD_ADC_SAMPLING                         0x212d
#define UART0_WFIFO                                0x2130
#define UART0_RFIFO                                0x2131
#define UART0_CONTROL                              0x2132
#define UART0_STATUS                               0x2133
#define UART0_MISC                                 0x2134
#define UART0_REG5                                 0x2135
#define UART1_WFIFO                                0x2137
#define UART1_RFIFO                                0x2138
#define UART1_CONTROL                              0x2139
#define UART1_STATUS                               0x213a
#define UART1_MISC                                 0x213b
#define UART1_REG5                                 0x213c
#define I2C_M_0_CONTROL_REG                        0x2140
#define I2C_M_0_SLAVE_ADDR                         0x2141
#define I2C_M_0_TOKEN_LIST0                        0x2142
#define I2C_M_0_TOKEN_LIST1                        0x2143
#define I2C_M_0_WDATA_REG0                         0x2144
#define I2C_M_0_WDATA_REG1                         0x2145
#define I2C_M_0_RDATA_REG0                         0x2146
#define I2C_M_0_RDATA_REG1                         0x2147
#define I2C_S_CONTROL_REG                          0x2150
#define I2C_S_SEND_REG                             0x2151
#define I2C_S_RECV_REG                             0x2152
#define I2C_S_CNTL1_REG                            0x2153
#define PWM_PWM_A                                  0x2154
#define PWM_PWM_B                                  0x2155
#define PWM_MISC_REG_AB                            0x2156
#define PWM_DELTA_SIGMA_AB                         0x2157
#define ATAPI_IDEREG0                              0x2160
#define ATAPI_IDEREG1                              0x2161
#define ATAPI_IDEREG2                              0x2162
#define ATAPI_CYCTIME                              0x2163
#define ATAPI_IDETIME                              0x2164
#define ATAPI_PIO_TIMING                           0x2165
#define ATAPI_TABLE_ADD_REG                        0x2166
#define ATAPI_IDEREG3                              0x2167
#define ATAPI_UDMA_REG0                            0x2168
#define ATAPI_UDMA_REG1                            0x2169
#define TRANS_PWMA_REG0                            0x2170
#define TRANS_PWMA_REG1                            0x2171
#define TRANS_PWMA_MUX0                            0x2172
#define TRANS_PWMA_MUX1                            0x2173
#define TRANS_PWMA_MUX2                            0x2174
#define TRANS_PWMA_MUX3                            0x2175
#define TRANS_PWMA_MUX4                            0x2176
#define TRANS_PWMA_MUX5                            0x2177
#define TRANS_PWMB_REG0                            0x2178
#define TRANS_PWMB_REG1                            0x2179
#define TRANS_PWMB_MUX0                            0x217a
#define TRANS_PWMB_MUX1                            0x217b
#define TRANS_PWMB_MUX2                            0x217c
#define TRANS_PWMB_MUX3                            0x217d
#define TRANS_PWMB_MUX4                            0x217e
#define TRANS_PWMB_MUX5                            0x217f
#define NAND_START                                 0x2180
#define NAND_ADR_CMD                               0x218a
#define NAND_ADR_STS                               0x218b
#define NAND_END                                   0x218f
#define PWM_PWM_C                                  0x2194
#define PWM_PWM_D                                  0x2195
#define PWM_MISC_REG_CD                            0x2196
#define PWM_DELTA_SIGMA_CD                         0x2197
#define SAR_ADC_REG0                               0x21a0
#define SAR_ADC_CHAN_LIST                          0x21a1
#define SAR_ADC_AVG_CNTL                           0x21a2
#define SAR_ADC_REG3                               0x21a3
#define SAR_ADC_DELAY                              0x21a4
#define SAR_ADC_LAST_RD                            0x21a5
#define SAR_ADC_FIFO_RD                            0x21a6
#define SAR_ADC_AUX_SW                             0x21a7
#define SAR_ADC_CHAN_10_SW                         0x21a8
#define SAR_ADC_DETECT_IDLE_SW                     0x21a9
#define SAR_ADC_DELTA_10                           0x21aa
#define CTOUCH_REG0                                0x21b0
#define CTOUCH_REG1                                0x21b1
#define CTOUCH_FIFO                                0x21b2
#define CTOUCH_REG3                                0x21b3
#define CTOUCH_INIT_CLK0                           0x21b4
#define CTOUCH_INIT_CLK1                           0x21b5
#define CTOUCH_REG6                                0x21b6
#define CTOUCH_GND_SW_MASK                         0x21b7
#define CTOUCH_MSR_TB_SEL                          0x21b8
#define CTOUCH_CAP_THRESH0                         0x21b9
#define CTOUCH_CAP_THRESH1                         0x21ba
#define CTOUCH_CHAN_LIST0                          0x21bb
#define CTOUCH_CHAN_LIST1                          0x21bc
#define CTOUCH_MSR_TB0                             0x21bd
#define CTOUCH_MSR_TB1                             0x21be
#define CTOUCH_REG15                               0x21bf
#define UART2_WFIFO                                0x21c0
#define UART2_RFIFO                                0x21c1
#define UART2_CONTROL                              0x21c2
#define UART2_STATUS                               0x21c3
#define UART2_MISC                                 0x21c4
#define UART2_REG5                                 0x21c5
#define UART3_WFIFO                                0x21c8
#define UART3_RFIFO                                0x21c9
#define UART3_CONTROL                              0x21ca
#define UART3_STATUS                               0x21cb
#define UART3_MISC                                 0x21cc
#define UART3_REG5                                 0x21cd
#define RTC_ADDR0                                  0x21d0
#define RTC_ADDR1                                  0x21d1
#define RTC_ADDR2                                  0x21d2
#define RTC_ADDR3                                  0x21d3
#define RTC_ADDR4                                  0x21d4
#define MSR_CLK_DUTY                               0x21d6
#define MSR_CLK_REG0                               0x21d7
#define MSR_CLK_REG1                               0x21d8
#define MSR_CLK_REG2                               0x21d9
#define LED_PWM_REG0                               0x21da
#define LED_PWM_REG1                               0x21db
#define LED_PWM_REG2                               0x21dc
#define LED_PWM_REG3                               0x21dd
#define LED_PWM_REG4                               0x21de
#define LED_PWM_REG5                               0x21df
#define LED_PWM_REG6                               0x21e0
#define VGHL_PWM_REG0                              0x21e1
#define VGHL_PWM_REG1                              0x21e2
#define VGHL_PWM_REG2                              0x21e3
#define VGHL_PWM_REG3                              0x21e4
#define VGHL_PWM_REG4                              0x21e5
#define VGHL_PWM_REG5                              0x21e6
#define VGHL_PWM_REG6                              0x21e7
#define I2C_M_1_CONTROL_REG                        0x21f0
#define I2C_M_1_SLAVE_ADDR                         0x21f1
#define I2C_M_1_TOKEN_LIST0                        0x21f2
#define I2C_M_1_TOKEN_LIST1                        0x21f3
#define I2C_M_1_WDATA_REG0                         0x21f4
#define I2C_M_1_WDATA_REG1                         0x21f5
#define I2C_M_1_RDATA_REG0                         0x21f6
#define I2C_M_1_RDATA_REG1                         0x21f7
#define I2C_M_2_CONTROL_REG                        0x21f8
#define I2C_M_2_SLAVE_ADDR                         0x21f9
#define I2C_M_2_TOKEN_LIST0                        0x21fa
#define I2C_M_2_TOKEN_LIST1                        0x21fb
#define I2C_M_2_WDATA_REG0                         0x21fc
#define I2C_M_2_WDATA_REG1                         0x21fd
#define I2C_M_2_RDATA_REG0                         0x21fe
#define I2C_M_2_RDATA_REG1                         0x21ff
#define BT_CTRL                                    0x2240
#define BT_VBISTART                                0x2241
#define BT_VBIEND                                  0x2242
#define BT_FIELDSADR                               0x2243
#define BT_LINECTRL                                0x2244
#define BT_VIDEOSTART                              0x2245
#define BT_VIDEOEND                                0x2246
#define BT_SLICELINE0                              0x2247
#define BT_SLICELINE1                              0x2248
#define BT_PORT_CTRL                               0x2249
#define BT_SWAP_CTRL                               0x224a
#define BT_ANCISADR                                0x224b
#define BT_ANCIEADR                                0x224c
#define BT_AFIFO_CTRL                              0x224d
#define BT_601_CTRL0                               0x224e
#define BT_601_CTRL1                               0x224f
#define BT_601_CTRL2                               0x2250
#define BT_601_CTRL3                               0x2251
#define BT_FIELD_LUMA                              0x2252
#define BT_RAW_CTRL                                0x2253
#define BT_STATUS                                  0x2254
#define BT_INT_CTRL                                0x2255
#define BT_ANCI_STATUS                             0x2256
#define BT_VLINE_STATUS                            0x2257
#define BT_AFIFO_PTR                               0x2258
#define BT_JPEGBYTENUM                             0x2259
#define BT_ERR_CNT                                 0x225a
#define BT_JPEG_STATUS0                            0x225b
#define BT_JPEG_STATUS1                            0x225c
#define BT_LCNT_STATUS                             0x225d
#define BT_PCNT_STATUS                             0x225e
#define BT656_ADDR_END                             0x225f
#define NDMA_CNTL_REG0                             0x2270
#define NDMA_TABLE_ADD_REG                         0x2272
#define NDMA_TDES_KEY_LO                           0x2273
#define NDMA_TDES_KEY_HI                           0x2274
#define NDMA_TDES_CONTROL                          0x2275
#define NDMA_AES_CONTROL                           0x2276
#define NDMA_AES_RK_FIFO                           0x2277
#define NDMA_CRC_OUT                               0x2278
#define NDMA_THREAD_REG                            0x2279
#define NDMA_THREAD_TABLE_START0                   0x2280
#define NDMA_THREAD_TABLE_CURR0                    0x2281
#define NDMA_THREAD_TABLE_END0                     0x2282
#define NDMA_THREAD_TABLE_START1                   0x2283
#define NDMA_THREAD_TABLE_CURR1                    0x2284
#define NDMA_THREAD_TABLE_END1                     0x2285
#define NDMA_THREAD_TABLE_START2                   0x2286
#define NDMA_THREAD_TABLE_CURR2                    0x2287
#define NDMA_THREAD_TABLE_END2                     0x2288
#define NDMA_THREAD_TABLE_START3                   0x2289
#define NDMA_THREAD_TABLE_CURR3                    0x228a
#define NDMA_THREAD_TABLE_END3                     0x228b
#define NDMA_CNTL_REG1                             0x228c
#define STREAM_EVENT_INFO                          0x2300
#define STREAM_OUTPUT_CONFIG                       0x2301
#define C_D_BUS_CONTROL                            0x2302
#define C_DATA                                     0x2303
#define STREAM_BUS_CONFIG                          0x2304
#define STREAM_DATA_IN_CONFIG                      0x2305
#define STREAM_WAIT_IRQ_CONFIG                     0x2306
#define STREAM_EVENT_CTL                           0x2307
#define CMD_ARGUMENT                               0x2308
#define CMD_SEND                                   0x2309
#define SDIO_CONFIG                                0x230a
#define SDIO_STATUS_IRQ                            0x230b
#define SDIO_IRQ_CONFIG                            0x230c
#define SDIO_MULT_CONFIG                           0x230d
#define SDIO_M_ADDR                                0x230e
#define SDIO_EXTENSION                             0x230f
#define ASYNC_FIFO_REG0                            0x2310
#define ASYNC_FIFO_REG1                            0x2311
#define ASYNC_FIFO_REG2                            0x2312
#define ASYNC_FIFO_REG3                            0x2313
#define ASYNC_FIFO2_REG0                           0x2314
#define ASYNC_FIFO2_REG1                           0x2315
#define ASYNC_FIFO2_REG2                           0x2316
#define ASYNC_FIFO2_REG3                           0x2317
#define SDIO_AHB_CBUS_CTRL                         0x2318
#define SDIO_AHB_CBUS_M_DATA                       0x2319
#define SPI_FLASH_CMD                              0x2320
#define SPI_FLASH_ADDR                             0x2321
#define SPI_FLASH_CTRL                             0x2322
#define SPI_FLASH_CTRL1                            0x2323
#define SPI_FLASH_STATUS                           0x2324
#define SPI_FLASH_CTRL2                            0x2325
#define SPI_FLASH_CLOCK                            0x2326
#define SPI_FLASH_USER                             0x2327
#define SPI_FLASH_USER1                            0x2328
#define SPI_FLASH_USER2                            0x2329
#define SPI_FLASH_USER3                            0x232a
#define SPI_FLASH_USER4                            0x232b
#define SPI_FLASH_SLAVE                            0x232c
#define SPI_FLASH_SLAVE1                           0x232d
#define SPI_FLASH_SLAVE2                           0x232e
#define SPI_FLASH_SLAVE3                           0x232f
#define SPI_FLASH_C0                               0x2330
#define SPI_FLASH_C1                               0x2331
#define SPI_FLASH_C2                               0x2332
#define SPI_FLASH_C3                               0x2333
#define SPI_FLASH_C4                               0x2334
#define SPI_FLASH_C5                               0x2335
#define SPI_FLASH_C6                               0x2336
#define SPI_FLASH_C7                               0x2337
#define SPI_FLASH_B8                               0x2338
#define SPI_FLASH_B9                               0x2339
#define SPI_FLASH_B10                              0x233a
#define SPI_FLASH_B11                              0x233b
#define SPI_FLASH_B12                              0x233c
#define SPI_FLASH_B13                              0x233d
#define SPI_FLASH_B14                              0x233e
#define SPI_FLASH_B15                              0x233f
#define SPICC_RXDATA                               0x2360
#define SPICC_TXDATA                               0x2361
#define SPICC_CONREG                               0x2362
#define SPICC_INTREG                               0x2363
#define SPICC_DMAREG                               0x2364
#define SPICC_STATREG                              0x2365
#define SPICC_PERIODREG                            0x2366
#define SPICC_TESTREG                              0x2367
#define SPICC_DRADDR                               0x2368
#define SPICC_DWADDR                               0x2369
#define SD_REG0_ARGU                               0x2380
#define SD_REG1_SEND                               0x2381
#define SD_REG2_CNTL                               0x2382
#define SD_REG3_STAT                               0x2383
#define SD_REG4_CLKC                               0x2384
#define SD_REG5_ADDR                               0x2385
#define SD_REG6_PDMA                               0x2386
#define SD_REG7_MISC                               0x2387
#define SD_REG8_DATA                               0x2388
#define SD_REG9_ICTL                               0x2389
#define SD_REGA_ISTA                               0x238a
#define SD_REGB_SRST                               0x238b
#define ISA_DEBUG_REG0                             0x2600
#define ISA_DEBUG_REG1                             0x2601
#define ISA_DEBUG_REG2                             0x2602
#define ISA_PLL_CLK_SIM0                           0x2608
#define ISA_CNTL_REG0                              0x2609
#define MEDIA_CPU_IRQ_IN0_INTR_STAT                0x2610
#define MEDIA_CPU_IRQ_IN0_INTR_STAT_CLR            0x2611
#define MEDIA_CPU_IRQ_IN0_INTR_MASK                0x2612
#define MEDIA_CPU_IRQ_IN0_INTR_FIRQ_SEL            0x2613
#define MEDIA_CPU_IRQ_IN1_INTR_STAT                0x2614
#define MEDIA_CPU_IRQ_IN1_INTR_STAT_CLR            0x2615
#define MEDIA_CPU_IRQ_IN1_INTR_MASK                0x2616
#define MEDIA_CPU_IRQ_IN1_INTR_FIRQ_SEL            0x2617
#define MEDIA_CPU_IRQ_IN2_INTR_STAT                0x2618
#define MEDIA_CPU_IRQ_IN2_INTR_STAT_CLR            0x2619
#define MEDIA_CPU_IRQ_IN2_INTR_MASK                0x261a
#define MEDIA_CPU_IRQ_IN2_INTR_FIRQ_SEL            0x261b
#define MEDIA_CPU_IRQ_IN3_INTR_STAT                0x261c
#define MEDIA_CPU_IRQ_IN3_INTR_STAT_CLR            0x261d
#define MEDIA_CPU_IRQ_IN3_INTR_MASK                0x261e
#define MEDIA_CPU_IRQ_IN3_INTR_FIRQ_SEL            0x261f
#define GPIO_INTR_EDGE_POL                         0x2620
#define GPIO_INTR_GPIO_SEL0                        0x2621
#define GPIO_INTR_GPIO_SEL1                        0x2622
#define GPIO_INTR_FILTER_SEL0                      0x2623
#define GLOBAL_INTR_DISABLE                        0x2624
#define WATCHDOG_TC                                0x2640
#define WATCHDOG_RESET                             0x2641
#define AHB_ARBITER_REG                            0x2642
#define AHB_ARBDEC_REG                             0x2643
#define AHB_ARBITER2_REG                           0x264a
#define DEVICE_MMCP_CNTL                           0x264b
#define AUDIO_MMCP_CNTL                            0x264c
#define ISA_BIST_REG0                              0x2644
#define ISA_BIST_REG1                              0x2645
#define ISA_BIST_REG2                              0x2646
#define ISA_BIST_REG3                              0x2647
#define ISA_BIST_REG4                              0x2648
#define ISA_BIST_REG5                              0x2649
#define ISA_BIST_REG6                              0x264e
#define ISA_TIMER_MUX                              0x2650
#define ISA_TIMERA                                 0x2651
#define ISA_TIMERB                                 0x2652
#define ISA_TIMERC                                 0x2653
#define ISA_TIMERD                                 0x2654
#define ISA_TIMERE                                 0x2655
#define FBUF_ADDR                                  0x2656
#define SDRAM_CTL0                                 0x2657
#define SDRAM_CTL2                                 0x2658
#define MEDIA_CPU_CTL                              0x2659
#define SDRAM_CTL4                                 0x265a
#define SDRAM_CTL5                                 0x265b
#define SDRAM_CTL6                                 0x265c
#define SDRAM_CTL7                                 0x265d
#define SDRAM_CTL8                                 0x265e
#define AHB_MP4_MC_CTL                             0x265f
#define MEDIA_CPU_PCR                              0x2660
#define ABUF_WR_CTL0                               0x2670
#define ABUF_WR_CTL1                               0x2671
#define ABUF_WR_CTL2                               0x2672
#define ABUF_WR_CTL3                               0x2673
#define ABUF_RD_CTL0                               0x2674
#define ABUF_RD_CTL1                               0x2675
#define ABUF_RD_CTL2                               0x2676
#define ABUF_RD_CTL3                               0x2677
#define ABUF_ARB_CTL0                              0x2678
#define ABUF_FIFO_CTL0                             0x2679
#define AHB_BRIDGE_CNTL_WR                         0x2680
#define AHB_BRIDGE_REMAP0                          0x2681
#define AHB_BRIDGE_REMAP1                          0x2682
#define AHB_BRIDGE_REMAP2                          0x2683
#define AHB_BRIDGE_REMAP3                          0x2684
#define AHB_BRIDGE_CNTL_REG1                       0x2685
#define SYS_CPU_0_IRQ_IN0_INTR_STAT                0x2690
#define SYS_CPU_0_IRQ_IN0_INTR_STAT_CLR            0x2691
#define SYS_CPU_0_IRQ_IN0_INTR_MASK                0x2692
#define SYS_CPU_0_IRQ_IN0_INTR_FIRQ_SEL            0x2693
#define SYS_CPU_0_IRQ_IN1_INTR_STAT                0x2694
#define SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR            0x2695
#define SYS_CPU_0_IRQ_IN1_INTR_MASK                0x2696
#define SYS_CPU_0_IRQ_IN1_INTR_FIRQ_SEL            0x2697
#define SYS_CPU_0_IRQ_IN2_INTR_STAT                0x2698
#define SYS_CPU_0_IRQ_IN2_INTR_STAT_CLR            0x2699
#define SYS_CPU_0_IRQ_IN2_INTR_MASK                0x269a
#define SYS_CPU_0_IRQ_IN2_INTR_FIRQ_SEL            0x269b
#define SYS_CPU_0_IRQ_IN3_INTR_STAT                0x269c
#define SYS_CPU_0_IRQ_IN3_INTR_STAT_CLR            0x269d
#define SYS_CPU_0_IRQ_IN3_INTR_MASK                0x269e
#define SYS_CPU_0_IRQ_IN3_INTR_FIRQ_SEL            0x269f
#define SYS_CPU_1_IRQ_IN0_INTR_STAT                0x26a0
#define SYS_CPU_1_IRQ_IN0_INTR_STAT_CLR            0x26a1
#define SYS_CPU_1_IRQ_IN0_INTR_MASK                0x26a2
#define SYS_CPU_1_IRQ_IN0_INTR_FIRQ_SEL            0x26a3
#define SYS_CPU_1_IRQ_IN1_INTR_STAT                0x26a4
#define SYS_CPU_1_IRQ_IN1_INTR_STAT_CLR            0x26a5
#define SYS_CPU_1_IRQ_IN1_INTR_MASK                0x26a6
#define SYS_CPU_1_IRQ_IN1_INTR_FIRQ_SEL            0x26a7
#define SYS_CPU_1_IRQ_IN2_INTR_STAT                0x26a8
#define SYS_CPU_1_IRQ_IN2_INTR_STAT_CLR            0x26a9
#define SYS_CPU_1_IRQ_IN2_INTR_MASK                0x26aa
#define SYS_CPU_1_IRQ_IN2_INTR_FIRQ_SEL            0x26ab
#define SYS_CPU_1_IRQ_IN3_INTR_STAT                0x26ac
#define SYS_CPU_1_IRQ_IN3_INTR_STAT_CLR            0x26ad
#define SYS_CPU_1_IRQ_IN3_INTR_MASK                0x26ae
#define SYS_CPU_1_IRQ_IN3_INTR_FIRQ_SEL            0x26af
#define MEDIA_CPU_IRQ_IN4_INTR_STAT                0x26b0
#define MEDIA_CPU_IRQ_IN4_INTR_STAT_CLR            0x26b1
#define MEDIA_CPU_IRQ_IN4_INTR_MASK                0x26b2
#define MEDIA_CPU_IRQ_IN4_INTR_FIRQ_SEL            0x26b3
#define SYS_CPU_0_IRQ_IN4_INTR_STAT                0x26b4
#define SYS_CPU_0_IRQ_IN4_INTR_STAT_CLR            0x26b5
#define SYS_CPU_0_IRQ_IN4_INTR_MASK                0x26b6
#define SYS_CPU_0_IRQ_IN4_INTR_FIRQ_SEL            0x26b7
#define SYS_CPU_1_IRQ_IN4_INTR_STAT                0x26b8
#define SYS_CPU_1_IRQ_IN4_INTR_STAT_CLR            0x26b9
#define SYS_CPU_1_IRQ_IN4_INTR_MASK                0x26ba
#define SYS_CPU_1_IRQ_IN4_INTR_FIRQ_SEL            0x26bb
#define IQ_OM_WIDTH                                0x2510
#define DBG_ADDR_START                             0x2ff0
#define DBG_ADDR_END                               0x2fff
#define DBG_CTRL                                   0x2ff1
#define DBG_LED                                    0x2ff2
#define DBG_SWITCH                                 0x2ff3
#define DBG_VERSION                                0x2ff4
#define VERSION_CTRL                               0x1100
#define RESET0_REGISTER                            0x1101
#define RESET1_REGISTER                            0x1102
#define RESET2_REGISTER                            0x1103
#define RESET3_REGISTER                            0x1104
#define RESET4_REGISTER                            0x1105
#define RESET5_REGISTER                            0x1106
#define RESET6_REGISTER                            0x1107
#define RESET0_MASK                                0x1110
#define RESET1_MASK                                0x1111
#define RESET2_MASK                                0x1112
#define RESET3_MASK                                0x1113
#define RESET4_MASK                                0x1114
#define RESET5_MASK                                0x1115
#define RESET6_MASK                                0x1116
#define CRT_MASK                                   0x1117
#define SCR_HIU                                    0x100b
#define HPG_TIMER                                  0x100f
#define HARM_ASB_MB0                               0x1030
#define HARM_ASB_MB1                               0x1031
#define HARM_ASB_MB2                               0x1032
#define HARM_ASB_MB3                               0x1033
#define HASB_ARM_MB0                               0x1034
#define HASB_ARM_MB1                               0x1035
#define HASB_ARM_MB2                               0x1036
#define HASB_ARM_MB3                               0x1037
#define HHI_TIMER90K                               0x103b
#define HHI_AUD_DAC_CTRL                           0x1044
#define HHI_VIID_PLL_CNTL4                         0x1046
#define HHI_VIID_PLL_CNTL                          0x1047
#define HHI_VIID_PLL_CNTL2                         0x1048
#define HHI_VIID_PLL_CNTL3                         0x1049
#define HHI_VIID_CLK_DIV                           0x104a
#define HHI_VIID_CLK_CNTL                          0x104b
#define HHI_VIID_DIVIDER_CNTL                      0x104c
#define HHI_GCLK_MPEG0                             0x1050
#define HHI_GCLK_MPEG1                             0x1051
#define HHI_GCLK_MPEG2                             0x1052
#define HHI_GCLK_OTHER                             0x1054
#define HHI_GCLK_AO                                0x1055
#define HHI_VID_CLK_DIV                            0x1059
#define HHI_MPEG_CLK_CNTL                          0x105d
#define HHI_AUD_CLK_CNTL                           0x105e
#define HHI_VID_CLK_CNTL                           0x105f
#define HHI_WIFI_CLK_CNTL                          0x1060
#define HHI_WIFI_PLL_CNTL                          0x1061
#define HHI_WIFI_PLL_CNTL2                         0x1062
#define HHI_WIFI_PLL_CNTL3                         0x1063
#define HHI_AUD_CLK_CNTL2                          0x1064
#define HHI_VID_DIVIDER_CNTL                       0x1066
#define HHI_SYS_CPU_CLK_CNTL                       0x1067
#define HHI_DDR_PLL_CNTL                           0x1068
#define HHI_DDR_PLL_CNTL2                          0x1069
#define HHI_DDR_PLL_CNTL3                          0x106a
#define HHI_DDR_PLL_CNTL4                          0x106b
#define HHI_MALI_CLK_CNTL                          0x106c
#define HHI_VDEC_CLK_CNTL                          0x106d
#define HHI_MIPI_PHY_CLK_CNTL                      0x106e
#define HHI_OTHER_PLL_CNTL                         0x1070
#define HHI_OTHER_PLL_CNTL2                        0x1071
#define HHI_OTHER_PLL_CNTL3                        0x1072
#define HHI_HDMI_CLK_CNTL                          0x1073
#define HHI_DEMOD_CLK_CNTL                         0x1074
#define HHI_SATA_CLK_CNTL                          0x1075
#define HHI_ETH_CLK_CNTL                           0x1076
#define HHI_CLK_DOUBLE_CNTL                        0x1077
#define HHI_SYS_CPU_AUTO_CLK0                      0x1078
#define HHI_SYS_CPU_AUTO_CLK1                      0x1079
#define HHI_MEDIA_CPU_AUTO_CLK0                    0x107a
#define HHI_MEDIA_CPU_AUTO_CLK1                    0x107b
#define HHI_HDMI_PLL_CNTL                          0x107c
#define HHI_HDMI_PLL_CNTL1                         0x107d
#define HHI_HDMI_PLL_CNTL2                         0x107e
#define HHI_HDMI_AFC_CNTL                          0x107f
#define HHI_VID_PLL_MOD_CNTL0                      0x1084
#define HHI_VID_PLL_MOD_LOW_TCNT                   0x1085
#define HHI_VID_PLL_MOD_HIGH_TCNT                  0x1086
#define HHI_VID_PLL_MOD_NOM_TCNT                   0x1087
#define HHI_DDR_CLK_CNTL                           0x1088
#define HHI_GEN_CLK_CNTL                           0x108a
#define HHI_GEN_CLK_CNTL2                          0x108b
#define HHI_JTAG_CONFIG                            0x108e
#define HHI_VAFE_CLKXTALIN_CNTL                    0x108f
#define HHI_VAFE_CLKOSCIN_CNTL                     0x1090
#define HHI_VAFE_CLKIN_CNTL                        0x1091
#define HHI_TVFE_AUTOMODE_CLK_CNTL                 0x1092
#define HHI_VAFE_CLKPI_CNTL                        0x1093
#define HHI_VDIN_MEAS_CLK_CNTL                     0x1094
#define HHI_PCM_CLK_CNTL                           0x1096
#define HHI_SYS_PLL_CNTL                           0x1098
#define HHI_SYS_PLL_CNTL2                          0x1099
#define HHI_SYS_PLL_CNTL3                          0x109a
#define HHI_SYS_PLL_CNTL4                          0x109b
#define HHI_VID_PLL_CNTL                           0x109c
#define HHI_VID_PLL_CNTL2                          0x109d
#define HHI_VID_PLL_CNTL3                          0x109e
#define HHI_VID_PLL_CNTL4                          0x109f
#define HHI_MPLL_CNTL                              0x10a0
#define HHI_MPLL_CNTL2                             0x10a1
#define HHI_MPLL_CNTL3                             0x10a2
#define HHI_MPLL_CNTL4                             0x10a3
#define HHI_MPLL_CNTL5                             0x10a4
#define HHI_MPLL_CNTL6                             0x10a5
#define HHI_MPLL_CNTL7                             0x10a6
#define HHI_MPLL_CNTL8                             0x10a7
#define HHI_MPLL_CNTL9                             0x10a8
#define HHI_MPLL_CNTL10                            0x10a9
#define PARSER_CONTROL                             0x2960
#define PARSER_FETCH_ADDR                          0x2961
#define PARSER_FETCH_CMD                           0x2962
#define PARSER_FETCH_STOP_ADDR                     0x2963
#define PARSER_FETCH_LEVEL                         0x2964
#define PARSER_CONFIG                              0x2965
#define PFIFO_WR_PTR                               0x2966
#define PFIFO_RD_PTR                               0x2967
#define PFIFO_DATA                                 0x2968
#define PARSER_SEARCH_PATTERN                      0x2969
#define PARSER_SEARCH_MASK                         0x296a
#define PARSER_INT_ENABLE                          0x296b
#define PARSER_INT_STATUS                          0x296c
#define PARSER_SCR_CTL                             0x296d
#define PARSER_SCR                                 0x296e
#define PARSER_PARAMETER                           0x296f
#define PARSER_INSERT_DATA                         0x2970
#define VAS_STREAM_ID                              0x2971
#define VIDEO_DTS                                  0x2972
#define VIDEO_PTS                                  0x2973
#define VIDEO_PTS_DTS_WR_PTR                       0x2974
#define AUDIO_PTS                                  0x2975
#define AUDIO_PTS_WR_PTR                           0x2976
#define PARSER_ES_CONTROL                          0x2977
#define PFIFO_MONITOR                              0x2978
#define PARSER_VIDEO_START_PTR                     0x2980
#define PARSER_VIDEO_END_PTR                       0x2981
#define PARSER_VIDEO_WP                            0x2982
#define PARSER_VIDEO_RP                            0x2983
#define PARSER_VIDEO_HOLE                          0x2984
#define PARSER_AUDIO_START_PTR                     0x2985
#define PARSER_AUDIO_END_PTR                       0x2986
#define PARSER_AUDIO_WP                            0x2987
#define PARSER_AUDIO_RP                            0x2988
#define PARSER_AUDIO_HOLE                          0x2989
#define PARSER_SUB_START_PTR                       0x298a
#define PARSER_SUB_END_PTR                         0x298b
#define PARSER_SUB_WP                              0x298c
#define PARSER_SUB_RP                              0x298d
#define PARSER_SUB_HOLE                            0x298e
#define PARSER_FETCH_INFO                          0x298f
#define PARSER_STATUS                              0x2990
#define PARSER_AV_WRAP_COUNT                       0x2991
#define WRRSP_PARSER                               0x2992
#define PARSER_VIDEO2_START_PTR                    0x2993
#define PARSER_VIDEO2_END_PTR                      0x2994
#define PARSER_VIDEO2_WP                           0x2995
#define PARSER_VIDEO2_RP                           0x2996
#define PARSER_VIDEO2_HOLE                         0x2997
#define PARSER_AV2_WRAP_COUNT                      0x2998
#define VDIN0_OFFSET            0x00
#define VDIN1_OFFSET            0x70
#define VDIN_SCALE_COEF_IDX                        0x1200
#define VDIN_SCALE_COEF                            0x1201
#define VDIN_COM_CTRL0                             0x1202
#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS             0x1203
#define VDIN_LCNT_STATUS                           0x1204
#define VDIN_COM_STATUS0                           0x1205
#define VDIN_COM_STATUS1                           0x1206
#define VDIN_LCNT_SHADOW_STATUS                    0x1207
#define VDIN_ASFIFO_CTRL0                          0x1208
#define VDIN_ASFIFO_CTRL1                          0x1209
#define VDIN_WIDTHM1I_WIDTHM1O                     0x120a
#define VDIN_SC_MISC_CTRL                          0x120b
#define VDIN_HSC_PHASE_STEP                        0x120c
#define VDIN_HSC_INI_CTRL                          0x120d
#define VDIN_COM_STATUS2                           0x120e
#define VDIN_ASFIFO_CTRL2                          0x120f
#define VDIN_MATRIX_CTRL                           0x1210
#define VDIN_MATRIX_COEF00_01                      0x1211
#define VDIN_MATRIX_COEF02_10                      0x1212
#define VDIN_MATRIX_COEF11_12                      0x1213
#define VDIN_MATRIX_COEF20_21                      0x1214
#define VDIN_MATRIX_COEF22                         0x1215
#define VDIN_MATRIX_OFFSET0_1                      0x1216
#define VDIN_MATRIX_OFFSET2                        0x1217
#define VDIN_MATRIX_PRE_OFFSET0_1                  0x1218
#define VDIN_MATRIX_PRE_OFFSET2                    0x1219
#define VDIN_LFIFO_CTRL                            0x121a
#define VDIN_COM_GCLK_CTRL                         0x121b
#define VDIN_INTF_WIDTHM1                          0x121c
#define VDIN_WR_CTRL2                              0x121f
#define VDIN_WR_CTRL                               0x1220
#define VDIN_WR_H_START_END                        0x1221
#define VDIN_WR_V_START_END                        0x1222
#define VDIN_HIST_CTRL                             0x1230
#define VDIN_HIST_H_START_END                      0x1231
#define VDIN_HIST_V_START_END                      0x1232
#define VDIN_HIST_MAX_MIN                          0x1233
#define VDIN_HIST_SPL_VAL                          0x1234
#define VDIN_HIST_SPL_PIX_CNT                      0x1235
#define VDIN_HIST_CHROMA_SUM                       0x1236
#define VDIN_DNLP_HIST00                           0x1237
#define VDIN_DNLP_HIST01                           0x1238
#define VDIN_DNLP_HIST02                           0x1239
#define VDIN_DNLP_HIST03                           0x123a
#define VDIN_DNLP_HIST04                           0x123b
#define VDIN_DNLP_HIST05                           0x123c
#define VDIN_DNLP_HIST06                           0x123d
#define VDIN_DNLP_HIST07                           0x123e
#define VDIN_DNLP_HIST08                           0x123f
#define VDIN_DNLP_HIST09                           0x1240
#define VDIN_DNLP_HIST10                           0x1241
#define VDIN_DNLP_HIST11                           0x1242
#define VDIN_DNLP_HIST12                           0x1243
#define VDIN_DNLP_HIST13                           0x1244
#define VDIN_DNLP_HIST14                           0x1245
#define VDIN_DNLP_HIST15                           0x1246
#define VDIN_DNLP_HIST16                           0x1247
#define VDIN_DNLP_HIST17                           0x1248
#define VDIN_DNLP_HIST18                           0x1249
#define VDIN_DNLP_HIST19                           0x124a
#define VDIN_DNLP_HIST20                           0x124b
#define VDIN_DNLP_HIST21                           0x124c
#define VDIN_DNLP_HIST22                           0x124d
#define VDIN_DNLP_HIST23                           0x124e
#define VDIN_DNLP_HIST24                           0x124f
#define VDIN_DNLP_HIST25                           0x1250
#define VDIN_DNLP_HIST26                           0x1251
#define VDIN_DNLP_HIST27                           0x1252
#define VDIN_DNLP_HIST28                           0x1253
#define VDIN_DNLP_HIST29                           0x1254
#define VDIN_DNLP_HIST30                           0x1255
#define VDIN_DNLP_HIST31                           0x1256
#define VDIN_MEAS_CTRL0                            0x125a
#define VDIN_MEAS_VS_COUNT_HI                      0x125b
#define VDIN_MEAS_VS_COUNT_LO                      0x125c
#define VDIN_MEAS_HS_RANGE                         0x125d
#define VDIN_MEAS_HS_COUNT                         0x125e
#define VDIN_BLKBAR_CTRL1                          0x125f
#define VDIN_BLKBAR_CTRL0                          0x1260
#define VDIN_BLKBAR_H_START_END                    0x1261
#define VDIN_BLKBAR_V_START_END                    0x1262
#define VDIN_BLKBAR_CNT_THRESHOLD                  0x1263
#define VDIN_BLKBAR_ROW_TH1_TH2                    0x1264
#define VDIN_BLKBAR_IND_LEFT_START_END             0x1265
#define VDIN_BLKBAR_IND_RIGHT_START_END            0x1266
#define VDIN_BLKBAR_IND_LEFT1_CNT                  0x1267
#define VDIN_BLKBAR_IND_LEFT2_CNT                  0x1268
#define VDIN_BLKBAR_IND_RIGHT1_CNT                 0x1269
#define VDIN_BLKBAR_IND_RIGHT2_CNT                 0x126a
#define VDIN_BLKBAR_STATUS0                        0x126b
#define VDIN_BLKBAR_STATUS1                        0x126c
#define VDIN_WIN_H_START_END                       0x126d
#define VDIN_WIN_V_START_END                       0x126e
#define VDIN_ASFIFO_CTRL3                          0x126f
#define DVIN_FRONT_END_CTRL                        0x12e0
#define DVIN_HS_LEAD_VS_ODD                        0x12e1
#define DVIN_ACTIVE_START_PIX                      0x12e2
#define DVIN_ACTIVE_START_LINE                     0x12e3
#define DVIN_DISPLAY_SIZE                          0x12e4
#define DVIN_CTRL_STAT                             0x12e5
#define VDEC_ASSIST_MMC_CTRL0                      0x0001
#define VDEC_ASSIST_MMC_CTRL1                      0x0002
#define VDEC_ASSIST_AMR1_INT0                      0x0025
#define VDEC_ASSIST_AMR1_INT1                      0x0026
#define VDEC_ASSIST_AMR1_INT2                      0x0027
#define VDEC_ASSIST_AMR1_INT3                      0x0028
#define VDEC_ASSIST_AMR1_INT4                      0x0029
#define VDEC_ASSIST_AMR1_INT5                      0x002a
#define VDEC_ASSIST_AMR1_INT6                      0x002b
#define VDEC_ASSIST_AMR1_INT7                      0x002c
#define VDEC_ASSIST_AMR1_INT8                      0x002d
#define VDEC_ASSIST_AMR1_INT9                      0x002e
#define VDEC_ASSIST_AMR1_INTA                      0x002f
#define VDEC_ASSIST_AMR1_INTB                      0x0030
#define VDEC_ASSIST_AMR1_INTC                      0x0031
#define VDEC_ASSIST_AMR1_INTD                      0x0032
#define VDEC_ASSIST_AMR1_INTE                      0x0033
#define VDEC_ASSIST_AMR1_INTF                      0x0034
#define VDEC_ASSIST_AMR2_INT0                      0x0035
#define VDEC_ASSIST_AMR2_INT1                      0x0036
#define VDEC_ASSIST_AMR2_INT2                      0x0037
#define VDEC_ASSIST_AMR2_INT3                      0x0038
#define VDEC_ASSIST_AMR2_INT4                      0x0039
#define VDEC_ASSIST_AMR2_INT5                      0x003a
#define VDEC_ASSIST_AMR2_INT6                      0x003b
#define VDEC_ASSIST_AMR2_INT7                      0x003c
#define VDEC_ASSIST_AMR2_INT8                      0x003d
#define VDEC_ASSIST_AMR2_INT9                      0x003e
#define VDEC_ASSIST_AMR2_INTA                      0x003f
#define VDEC_ASSIST_AMR2_INTB                      0x0040
#define VDEC_ASSIST_AMR2_INTC                      0x0041
#define VDEC_ASSIST_AMR2_INTD                      0x0042
#define VDEC_ASSIST_AMR2_INTE                      0x0043
#define VDEC_ASSIST_AMR2_INTF                      0x0044
#define VDEC_ASSIST_TIMER0_LO                      0x0060
#define VDEC_ASSIST_TIMER0_HI                      0x0061
#define VDEC_ASSIST_TIMER1_LO                      0x0062
#define VDEC_ASSIST_TIMER1_HI                      0x0063
#define VDEC_ASSIST_DMA_INT                        0x0064
#define VDEC_ASSIST_DMA_INT_MSK                    0x0065
#define VDEC_ASSIST_DMA_INT2                       0x0066
#define VDEC_ASSIST_DMA_INT_MSK2                   0x0067
#define VDEC_ASSIST_MBOX0_IRQ_REG                  0x0070
#define VDEC_ASSIST_MBOX0_CLR_REG                  0x0071
#define VDEC_ASSIST_MBOX0_MASK                     0x0072
#define VDEC_ASSIST_MBOX0_FIQ_SEL                  0x0073
#define VDEC_ASSIST_MBOX1_IRQ_REG                  0x0074
#define VDEC_ASSIST_MBOX1_CLR_REG                  0x0075
#define VDEC_ASSIST_MBOX1_MASK                     0x0076
#define VDEC_ASSIST_MBOX1_FIQ_SEL                  0x0077
#define VDEC_ASSIST_MBOX2_IRQ_REG                  0x0078
#define VDEC_ASSIST_MBOX2_CLR_REG                  0x0079
#define VDEC_ASSIST_MBOX2_MASK                     0x007a
#define VDEC_ASSIST_MBOX2_FIQ_SEL                  0x007b
#define MC_CTRL_REG                                0x0900
#define MC_MB_INFO                                 0x0901
#define MC_PIC_INFO                                0x0902
#define MC_HALF_PEL_ONE                            0x0903
#define MC_HALF_PEL_TWO                            0x0904
#define POWER_CTL_MC                               0x0905
#define MC_CMD                                     0x0906
#define MC_CTRL0                                   0x0907
#define MC_PIC_W_H                                 0x0908
#define MC_STATUS0                                 0x0909
#define MC_STATUS1                                 0x090a
#define MC_CTRL1                                   0x090b
#define MC_MIX_RATIO0                              0x090c
#define MC_MIX_RATIO1                              0x090d
#define MC_DP_MB_XY                                0x090e
#define MC_OM_MB_XY                                0x090f
#define PSCALE_RST                                 0x0910
#define PSCALE_CTRL                                0x0911
#define PSCALE_PICI_W                              0x0912
#define PSCALE_PICI_H                              0x0913
#define PSCALE_PICO_W                              0x0914
#define PSCALE_PICO_H                              0x0915
#define PSCALE_PICO_START_X                        0x0916
#define PSCALE_PICO_START_Y                        0x0917
#define PSCALE_DUMMY                               0x0918
#define PSCALE_FILT0_COEF0                         0x0919
#define PSCALE_FILT0_COEF1                         0x091a
#define PSCALE_CMD_CTRL                            0x091b
#define PSCALE_CMD_BLK_X                           0x091c
#define PSCALE_CMD_BLK_Y                           0x091d
#define PSCALE_STATUS                              0x091e
#define PSCALE_BMEM_ADDR                           0x091f
#define PSCALE_BMEM_DAT                            0x0920
#define PSCALE_DRAM_BUF_CTRL                       0x0921
#define PSCALE_MCMD_CTRL                           0x0922
#define PSCALE_MCMD_XSIZE                          0x0923
#define PSCALE_MCMD_YSIZE                          0x0924
#define PSCALE_RBUF_START_BLKX                     0x0925
#define PSCALE_RBUF_START_BLKY                     0x0926
#define PSCALE_PICO_SHIFT_XY                       0x0928
#define PSCALE_CTRL1                               0x0929
#define PSCALE_SRCKEY_CTRL0                        0x092a
#define PSCALE_SRCKEY_CTRL1                        0x092b
#define PSCALE_CANVAS_RD_ADDR                      0x092c
#define PSCALE_CANVAS_WR_ADDR                      0x092d
#define PSCALE_CTRL2                               0x092e
#define MC_MPORT_CTRL                              0x0940
#define MC_MPORT_DAT                               0x0941
#define MC_WT_PRED_CTRL                            0x0942
#define MC_MBBOT_ST_EVEN_ADDR                      0x0944
#define MC_MBBOT_ST_ODD_ADDR                       0x0945
#define MC_DPDN_MB_XY                              0x0946
#define MC_OMDN_MB_XY                              0x0947
#define MC_HCMDBUF_H                               0x0948
#define MC_HCMDBUF_L                               0x0949
#define MC_HCMD_H                                  0x094a
#define MC_HCMD_L                                  0x094b
#define MC_IDCT_DAT                                0x094c
#define MC_CTRL_GCLK_CTRL                          0x094d
#define MC_OTHER_GCLK_CTRL                         0x094e
#define MC_CTRL2                                   0x094f
#define MDEC_PIC_DC_CTRL                           0x098e
#define MDEC_PIC_DC_STATUS                         0x098f
#define ANC0_CANVAS_ADDR                           0x0990
#define ANC1_CANVAS_ADDR                           0x0991
#define ANC2_CANVAS_ADDR                           0x0992
#define ANC3_CANVAS_ADDR                           0x0993
#define ANC4_CANVAS_ADDR                           0x0994
#define ANC5_CANVAS_ADDR                           0x0995
#define ANC6_CANVAS_ADDR                           0x0996
#define ANC7_CANVAS_ADDR                           0x0997
#define ANC8_CANVAS_ADDR                           0x0998
#define ANC9_CANVAS_ADDR                           0x0999
#define ANC10_CANVAS_ADDR                          0x099a
#define ANC11_CANVAS_ADDR                          0x099b
#define ANC12_CANVAS_ADDR                          0x099c
#define ANC13_CANVAS_ADDR                          0x099d
#define ANC14_CANVAS_ADDR                          0x099e
#define ANC15_CANVAS_ADDR                          0x099f
#define ANC16_CANVAS_ADDR                          0x09a0
#define ANC17_CANVAS_ADDR                          0x09a1
#define ANC18_CANVAS_ADDR                          0x09a2
#define ANC19_CANVAS_ADDR                          0x09a3
#define ANC20_CANVAS_ADDR                          0x09a4
#define ANC21_CANVAS_ADDR                          0x09a5
#define ANC22_CANVAS_ADDR                          0x09a6
#define ANC23_CANVAS_ADDR                          0x09a7
#define ANC24_CANVAS_ADDR                          0x09a8
#define ANC25_CANVAS_ADDR                          0x09a9
#define ANC26_CANVAS_ADDR                          0x09aa
#define ANC27_CANVAS_ADDR                          0x09ab
#define ANC28_CANVAS_ADDR                          0x09ac
#define ANC29_CANVAS_ADDR                          0x09ad
#define ANC30_CANVAS_ADDR                          0x09ae
#define ANC31_CANVAS_ADDR                          0x09af
#define DBKR_CANVAS_ADDR                           0x09b0
#define DBKW_CANVAS_ADDR                           0x09b1
#define REC_CANVAS_ADDR                            0x09b2
#define CURR_CANVAS_CTRL                           0x09b3
#define MDEC_PIC_DC_THRESH                         0x09b8
#define MDEC_PICR_BUF_STATUS                       0x09b9
#define MDEC_PICW_BUF_STATUS                       0x09ba
#define MCW_DBLK_WRRSP_CNT                         0x09bb
#define AV_SCRATCH_0                               0x09c0
#define AV_SCRATCH_1                               0x09c1
#define AV_SCRATCH_2                               0x09c2
#define AV_SCRATCH_3                               0x09c3
#define AV_SCRATCH_4                               0x09c4
#define AV_SCRATCH_5                               0x09c5
#define AV_SCRATCH_6                               0x09c6
#define AV_SCRATCH_7                               0x09c7
#define AV_SCRATCH_8                               0x09c8
#define AV_SCRATCH_9                               0x09c9
#define AV_SCRATCH_A                               0x09ca
#define AV_SCRATCH_B                               0x09cb
#define AV_SCRATCH_C                               0x09cc
#define AV_SCRATCH_D                               0x09cd
#define AV_SCRATCH_E                               0x09ce
#define AV_SCRATCH_F                               0x09cf
#define AV_SCRATCH_G                               0x09d0
#define AV_SCRATCH_H                               0x09d1
#define AV_SCRATCH_I                               0x09d2
#define AV_SCRATCH_J                               0x09d3
#define AV_SCRATCH_K                               0x09d4
#define AV_SCRATCH_L                               0x09d5
#define AV_SCRATCH_M                               0x09d6
#define AV_SCRATCH_N                               0x09d7
#define WRRSP_CO_MB                                0x09d8
#define WRRSP_DCAC                                 0x09d9
#define DBLK_RST                                   0x0950
#define DBLK_CTRL                                  0x0951
#define DBLK_MB_WID_HEIGHT                         0x0952
#define DBLK_STATUS                                0x0953
#define DBLK_CMD_CTRL                              0x0954
#define DBLK_MB_XY                                 0x0955
#define DBLK_QP                                    0x0956
#define DBLK_Y_BHFILT                              0x0957
#define DBLK_Y_BHFILT_HIGH                         0x0958
#define DBLK_Y_BVFILT                              0x0959
#define DBLK_CB_BFILT                              0x095a
#define DBLK_CR_BFILT                              0x095b
#define DBLK_Y_HFILT                               0x095c
#define DBLK_Y_HFILT_HIGH                          0x095d
#define DBLK_Y_VFILT                               0x095e
#define DBLK_CB_FILT                               0x095f
#define DBLK_CR_FILT                               0x0960
#define DBLK_BETAX_QP_SEL                          0x0961
#define DBLK_CLIP_CTRL0                            0x0962
#define DBLK_CLIP_CTRL1                            0x0963
#define DBLK_CLIP_CTRL2                            0x0964
#define DBLK_CLIP_CTRL3                            0x0965
#define DBLK_CLIP_CTRL4                            0x0966
#define DBLK_CLIP_CTRL5                            0x0967
#define DBLK_CLIP_CTRL6                            0x0968
#define DBLK_CLIP_CTRL7                            0x0969
#define DBLK_CLIP_CTRL8                            0x096a
#define DBLK_STATUS1                               0x096b
#define DBLK_GCLK_FREE                             0x096c
#define DBLK_GCLK_OFF                              0x096d
#define DBLK_AVSFLAGS                              0x096e
#define DBLK_CBPY                                  0x0970
#define DBLK_CBPY_ADJ                              0x0971
#define DBLK_CBPC                                  0x0972
#define DBLK_CBPC_ADJ                              0x0973
#define DBLK_VHMVD                                 0x0974
#define DBLK_STRONG                                0x0975
#define DBLK_RV8_QUANT                             0x0976
#define DBLK_CBUS_HCMD2                            0x0977
#define DBLK_CBUS_HCMD1                            0x0978
#define DBLK_CBUS_HCMD0                            0x0979
#define DBLK_VLD_HCMD2                             0x097a
#define DBLK_VLD_HCMD1                             0x097b
#define DBLK_VLD_HCMD0                             0x097c
#define DBLK_OST_YBASE                             0x097d
#define DBLK_OST_CBCRDIFF                          0x097e
#define DBLK_CTRL1                                 0x097f
#define VLD_STATUS_CTRL                            0x0c00
#define MPEG1_2_REG                                0x0c01
#define F_CODE_REG                                 0x0c02
#define PIC_HEAD_INFO                              0x0c03
#define SLICE_VER_POS_PIC_TYPE                     0x0c04
#define QP_VALUE_REG                               0x0c05
#define MBA_INC                                    0x0c06
#define MB_MOTION_MODE                             0x0c07
#define POWER_CTL_VLD                              0x0c08
#define MB_WIDTH                                   0x0c09
#define SLICE_QP                                   0x0c0a
#define PRE_START_CODE                             0x0c0b
#define SLICE_START_BYTE_01                        0x0c0c
#define SLICE_START_BYTE_23                        0x0c0d
#define RESYNC_MARKER_LENGTH                       0x0c0e
#define DECODER_BUFFER_INFO                        0x0c0f
#define FST_FOR_MV_X                               0x0c10
#define FST_FOR_MV_Y                               0x0c11
#define SCD_FOR_MV_X                               0x0c12
#define SCD_FOR_MV_Y                               0x0c13
#define FST_BAK_MV_X                               0x0c14
#define FST_BAK_MV_Y                               0x0c15
#define SCD_BAK_MV_X                               0x0c16
#define SCD_BAK_MV_Y                               0x0c17
#define VLD_DECODE_CONTROL                         0x0c18
#define VLD_REVERVED_19                            0x0c19
#define VIFF_BIT_CNT                               0x0c1a
#define BYTE_ALIGN_PEAK_HI                         0x0c1b
#define BYTE_ALIGN_PEAK_LO                         0x0c1c
#define NEXT_ALIGN_PEAK                            0x0c1d
#define VC1_CONTROL_REG                            0x0c1e
#define PMV1_X                                     0x0c20
#define PMV1_Y                                     0x0c21
#define PMV2_X                                     0x0c22
#define PMV2_Y                                     0x0c23
#define PMV3_X                                     0x0c24
#define PMV3_Y                                     0x0c25
#define PMV4_X                                     0x0c26
#define PMV4_Y                                     0x0c27
#define M4_TABLE_SELECT                            0x0c28
#define M4_CONTROL_REG                             0x0c29
#define BLOCK_NUM                                  0x0c2a
#define PATTERN_CODE                               0x0c2b
#define MB_INFO                                    0x0c2c
#define VLD_DC_PRED                                0x0c2d
#define VLD_ERROR_MASK                             0x0c2e
#define VLD_DC_PRED_C                              0x0c2f
#define LAST_SLICE_MV_ADDR                         0x0c30
#define LAST_MVX                                   0x0c31
#define LAST_MVY                                   0x0c32
#define VLD_C38                                    0x0c38
#define VLD_C39                                    0x0c39
#define VLD_STATUS                                 0x0c3a
#define VLD_SHIFT_STATUS                           0x0c3b
#define VOFF_STATUS                                0x0c3c
#define VLD_C3D                                    0x0c3d
#define VLD_DBG_INDEX                              0x0c3e
#define VLD_DBG_DATA                               0x0c3f
#define VLD_MEM_VIFIFO_START_PTR                   0x0c40
#define VLD_MEM_VIFIFO_CURR_PTR                    0x0c41
#define VLD_MEM_VIFIFO_END_PTR                     0x0c42
#define VLD_MEM_VIFIFO_BYTES_AVAIL                 0x0c43
#define VLD_MEM_VIFIFO_CONTROL                     0x0c44
#define VLD_MEM_VIFIFO_WP                          0x0c45
#define VLD_MEM_VIFIFO_RP                          0x0c46
#define VLD_MEM_VIFIFO_LEVEL                       0x0c47
#define VLD_MEM_VIFIFO_BUF_CNTL                    0x0c48
#define VLD_TIME_STAMP_CNTL                        0x0c49
#define VLD_TIME_STAMP_SYNC_0                      0x0c4a
#define VLD_TIME_STAMP_SYNC_1                      0x0c4b
#define VLD_TIME_STAMP_0                           0x0c4c
#define VLD_TIME_STAMP_1                           0x0c4d
#define VLD_TIME_STAMP_2                           0x0c4e
#define VLD_TIME_STAMP_3                           0x0c4f
#define VLD_TIME_STAMP_LENGTH                      0x0c50
#define VLD_MEM_VIFIFO_WRAP_COUNT                  0x0c51
#define VLD_MEM_VIFIFO_MEM_CTL                     0x0c52
#define VLD_MEM_VBUF_RD_PTR                        0x0c53
#define VLD_MEM_VBUF2_RD_PTR                       0x0c54
#define VLD_MEM_SWAP_ADDR                          0x0c55
#define VLD_MEM_SWAP_CTL                           0x0c56
#define VCOP_CTRL_REG                              0x0e00
#define QP_CTRL_REG                                0x0e01
#define INTRA_QUANT_MATRIX                         0x0e02
#define NON_I_QUANT_MATRIX                         0x0e03
#define DC_SCALER                                  0x0e04
#define DC_AC_CTRL                                 0x0e05
#define DC_AC_SCALE_MUL                            0x0e06
#define DC_AC_SCALE_DIV                            0x0e07
#define POWER_CTL_IQIDCT                           0x0e08
#define RV_AI_Y_X                                  0x0e09
#define RV_AI_U_X                                  0x0e0a
#define RV_AI_V_X                                  0x0e0b
#define RV_AI_MB_COUNT                             0x0e0c
#define NEXT_INTRA_DMA_ADDRESS                     0x0e0d
#define IQIDCT_CONTROL                             0x0e0e
#define IQIDCT_DEBUG_INFO_0                        0x0e0f
#define DEBLK_CMD                                  0x0e10
#define IQIDCT_DEBUG_IDCT                          0x0e11
#define DCAC_DMA_CTRL                              0x0e12
#define DCAC_DMA_ADDRESS                           0x0e13
#define DCAC_CPU_ADDRESS                           0x0e14
#define DCAC_CPU_DATA                              0x0e15
#define DCAC_MB_COUNT                              0x0e16
#define IQ_QUANT                                   0x0e17
#define VC1_BITPLANE_CTL                           0x0e18
#define MSP                                        0x0300
#define MPSR                                       0x0301
#define MINT_VEC_BASE                              0x0302
#define MCPU_INTR_GRP                              0x0303
#define MCPU_INTR_MSK                              0x0304
#define MCPU_INTR_REQ                              0x0305
#define MPC_P                                      0x0306
#define MPC_D                                      0x0307
#define MPC_E                                      0x0308
#define MPC_W                                      0x0309
#define MINDEX0_REG                                0x030a
#define MINDEX1_REG                                0x030b
#define MINDEX2_REG                                0x030c
#define MINDEX3_REG                                0x030d
#define MINDEX4_REG                                0x030e
#define MINDEX5_REG                                0x030f
#define MINDEX6_REG                                0x0310
#define MINDEX7_REG                                0x0311
#define MMIN_REG                                   0x0312
#define MMAX_REG                                   0x0313
#define MBREAK0_REG                                0x0314
#define MBREAK1_REG                                0x0315
#define MBREAK2_REG                                0x0316
#define MBREAK3_REG                                0x0317
#define MBREAK_TYPE                                0x0318
#define MBREAK_CTRL                                0x0319
#define MBREAK_STAUTS                              0x031a
#define MDB_ADDR_REG                               0x031b
#define MDB_DATA_REG                               0x031c
#define MDB_CTRL                                   0x031d
#define MSFTINT0                                   0x031e
#define MSFTINT1                                   0x031f
#define CSP                                        0x0320
#define CPSR                                       0x0321
#define CINT_VEC_BASE                              0x0322
#define CCPU_INTR_GRP                              0x0323
#define CCPU_INTR_MSK                              0x0324
#define CCPU_INTR_REQ                              0x0325
#define CPC_P                                      0x0326
#define CPC_D                                      0x0327
#define CPC_E                                      0x0328
#define CPC_W                                      0x0329
#define CINDEX0_REG                                0x032a
#define CINDEX1_REG                                0x032b
#define CINDEX2_REG                                0x032c
#define CINDEX3_REG                                0x032d
#define CINDEX4_REG                                0x032e
#define CINDEX5_REG                                0x032f
#define CINDEX6_REG                                0x0330
#define CINDEX7_REG                                0x0331
#define CMIN_REG                                   0x0332
#define CMAX_REG                                   0x0333
#define CBREAK0_REG                                0x0334
#define CBREAK1_REG                                0x0335
#define CBREAK2_REG                                0x0336
#define CBREAK3_REG                                0x0337
#define CBREAK_TYPE                                0x0338
#define CBREAK_CTRL                                0x0339
#define CBREAK_STAUTS                              0x033a
#define CDB_ADDR_REG                               0x033b
#define CDB_DATA_REG                               0x033c
#define CDB_CTRL                                   0x033d
#define CSFTINT0                                   0x033e
#define CSFTINT1                                   0x033f
#define IMEM_DMA_CTRL                              0x0340
#define IMEM_DMA_ADR                               0x0341
#define IMEM_DMA_COUNT                             0x0342
#define WRRSP_IMEM                                 0x0343
#define LMEM_DMA_CTRL                              0x0350
#define LMEM_DMA_ADR                               0x0351
#define LMEM_DMA_COUNT                             0x0352
#define WRRSP_LMEM                                 0x0353
#define MAC_CTRL1                                  0x0360
#define ACC0REG1                                   0x0361
#define ACC1REG1                                   0x0362
#define MAC_CTRL2                                  0x0370
#define ACC0REG2                                   0x0371
#define ACC1REG2                                   0x0372
#define CPU_TRACE                                  0x0380
#define DOS_SW_RESET0                              0x3f00
#define DOS_GCLK_EN0                               0x3f01
#define DOS_GEN_CTRL0                              0x3f02
#define DOS_APB_ERR_CTRL                           0x3f03
#define DOS_APB_ERR_STAT                           0x3f04
#define DOS_SCRATCH0                               0x3f10
#define DOS_SCRATCH1                               0x3f11
#define DOS_SCRATCH2                               0x3f12
#define DOS_SCRATCH3                               0x3f13
#define DOS_SCRATCH4                               0x3f14
#define DOS_SCRATCH5                               0x3f15
#define DOS_SCRATCH6                               0x3f16
#define DOS_SCRATCH7                               0x3f17
#define DOS_SCRATCH8                               0x3f18
#define DOS_SCRATCH9                               0x3f19
#define DOS_SCRATCH10                              0x3f1a
#define DOS_SCRATCH11                              0x3f1b
#define DOS_SCRATCH12                              0x3f1c
#define DOS_SCRATCH13                              0x3f1d
#define DOS_SCRATCH14                              0x3f1e
#define DOS_SCRATCH15                              0x3f1f
#define DOS_SCRATCH16                              0x3f20
#define DOS_SCRATCH17                              0x3f21
#define DOS_SCRATCH18                              0x3f22
#define DOS_SCRATCH19                              0x3f23
#define DOS_SCRATCH20                              0x3f24
#define DOS_SCRATCH21                              0x3f25
#define DOS_SCRATCH22                              0x3f26
#define DOS_SCRATCH23                              0x3f27
#define DOS_SCRATCH24                              0x3f28
#define DOS_SCRATCH25                              0x3f29
#define DOS_SCRATCH26                              0x3f2a
#define DOS_SCRATCH27                              0x3f2b
#define DOS_SCRATCH28                              0x3f2c
#define DOS_SCRATCH29                              0x3f2d
#define DOS_SCRATCH30                              0x3f2e
#define DOS_SCRATCH31                              0x3f2f
#define AIU_958_BPF                                0x1500
#define AIU_958_BRST                               0x1501
#define AIU_958_LENGTH                             0x1502
#define AIU_958_PADDSIZE                           0x1503
#define AIU_958_MISC                               0x1504
#define AIU_958_FORCE_LEFT                         0x1505
#define AIU_958_DISCARD_NUM                        0x1506
#define AIU_958_DCU_FF_CTRL                        0x1507
#define AIU_958_CHSTAT_L0                          0x1508
#define AIU_958_CHSTAT_L1                          0x1509
#define AIU_958_CTRL                               0x150a
#define AIU_958_RPT                                0x150b
#define AIU_I2S_MUTE_SWAP                          0x150c
#define AIU_I2S_SOURCE_DESC                        0x150d
#define AIU_I2S_MED_CTRL                           0x150e
#define AIU_I2S_MED_THRESH                         0x150f
#define AIU_I2S_DAC_CFG                            0x1510
#define AIU_I2S_SYNC                               0x1511
#define AIU_I2S_MISC                               0x1512
#define AIU_I2S_OUT_CFG                            0x1513
#define AIU_I2S_FF_CTRL                            0x1514
#define AIU_RST_SOFT                               0x1515
#define AIU_CLK_CTRL                               0x1516
#define AIU_MIX_ADCCFG                             0x1517
#define AIU_MIX_CTRL                               0x1518
#define AIU_CLK_CTRL_MORE                          0x1519
#define AIU_958_POP                                0x151a
#define AIU_MIX_GAIN                               0x151b
#define AIU_958_SYNWORD1                           0x151c
#define AIU_958_SYNWORD2                           0x151d
#define AIU_958_SYNWORD3                           0x151e
#define AIU_958_SYNWORD1_MASK                      0x151f
#define AIU_958_SYNWORD2_MASK                      0x1520
#define AIU_958_SYNWORD3_MASK                      0x1521
#define AIU_958_FFRDOUT_THD                        0x1522
#define AIU_958_LENGTH_PER_PAUSE                   0x1523
#define AIU_958_PAUSE_NUM                          0x1524
#define AIU_958_PAUSE_PAYLOAD                      0x1525
#define AIU_958_AUTO_PAUSE                         0x1526
#define AIU_958_PAUSE_PD_LENGTH                    0x1527
#define AIU_CODEC_DAC_LRCLK_CTRL                   0x1528
#define AIU_CODEC_ADC_LRCLK_CTRL                   0x1529
#define AIU_HDMI_CLK_DATA_CTRL                     0x152a
#define AIU_CODEC_CLK_DATA_CTRL                    0x152b
#define AIU_958_CHSTAT_R0                          0x1530
#define AIU_958_CHSTAT_R1                          0x1531
#define AIU_958_VALID_CTRL                         0x1532
#define AIU_AUDIO_AMP_REG0                         0x153c
#define AIU_AUDIO_AMP_REG1                         0x153d
#define AIU_AUDIO_AMP_REG2                         0x153e
#define AIU_AUDIO_AMP_REG3                         0x153f
#define AIU_AIFIFO2_CTRL                           0x1540
#define AIU_AIFIFO2_STATUS                         0x1541
#define AIU_AIFIFO2_GBIT                           0x1542
#define AIU_AIFIFO2_CLB                            0x1543
#define AIU_CRC_CTRL                               0x1544
#define AIU_CRC_STATUS                             0x1545
#define AIU_CRC_SHIFT_REG                          0x1546
#define AIU_CRC_IREG                               0x1547
#define AIU_CRC_CAL_REG1                           0x1548
#define AIU_CRC_CAL_REG0                           0x1549
#define AIU_CRC_POLY_COEF1                         0x154a
#define AIU_CRC_POLY_COEF0                         0x154b
#define AIU_CRC_BIT_SIZE1                          0x154c
#define AIU_CRC_BIT_SIZE0                          0x154d
#define AIU_CRC_BIT_CNT1                           0x154e
#define AIU_CRC_BIT_CNT0                           0x154f
#define AIU_AMCLK_GATE_HI                          0x1550
#define AIU_AMCLK_GATE_LO                          0x1551
#define AIU_AMCLK_MSR                              0x1552
#define AIU_AUDAC_CTRL0                            0x1553
#define AIU_AUDAC_CTRL1                            0x1554
#define AIU_DELTA_SIGMA0                           0x1555
#define AIU_DELTA_SIGMA1                           0x1556
#define AIU_DELTA_SIGMA2                           0x1557
#define AIU_DELTA_SIGMA3                           0x1558
#define AIU_DELTA_SIGMA4                           0x1559
#define AIU_DELTA_SIGMA5                           0x155a
#define AIU_DELTA_SIGMA6                           0x155b
#define AIU_DELTA_SIGMA7                           0x155c
#define AIU_DELTA_SIGMA_LCNTS                      0x155d
#define AIU_DELTA_SIGMA_RCNTS                      0x155e
#define AIU_MEM_I2S_START_PTR                      0x1560
#define AIU_MEM_I2S_RD_PTR                         0x1561
#define AIU_MEM_I2S_END_PTR                        0x1562
#define AIU_MEM_I2S_MASKS                          0x1563
#define AIU_MEM_I2S_CONTROL                        0x1564
#define AIU_MEM_IEC958_START_PTR                   0x1565
#define AIU_MEM_IEC958_RD_PTR                      0x1566
#define AIU_MEM_IEC958_END_PTR                     0x1567
#define AIU_MEM_IEC958_MASKS                       0x1568
#define AIU_MEM_IEC958_CONTROL                     0x1569
#define AIU_MEM_AIFIFO2_START_PTR                  0x156a
#define AIU_MEM_AIFIFO2_CURR_PTR                   0x156b
#define AIU_MEM_AIFIFO2_END_PTR                    0x156c
#define AIU_MEM_AIFIFO2_BYTES_AVAIL                0x156d
#define AIU_MEM_AIFIFO2_CONTROL                    0x156e
#define AIU_MEM_AIFIFO2_MAN_WP                     0x156f
#define AIU_MEM_AIFIFO2_MAN_RP                     0x1570
#define AIU_MEM_AIFIFO2_LEVEL                      0x1571
#define AIU_MEM_AIFIFO2_BUF_CNTL                   0x1572
#define AIU_MEM_I2S_MAN_WP                         0x1573
#define AIU_MEM_I2S_MAN_RP                         0x1574
#define AIU_MEM_I2S_LEVEL                          0x1575
#define AIU_MEM_I2S_BUF_CNTL                       0x1576
#define AIU_MEM_I2S_BUF_WRAP_COUNT                 0x1577
#define AIU_MEM_I2S_MEM_CTL                        0x1578
#define AIU_MEM_IEC958_MEM_CTL                     0x1579
#define AIU_MEM_IEC958_WRAP_COUNT                  0x157a
#define AIU_MEM_IEC958_IRQ_LEVEL                   0x157b
#define AIU_MEM_IEC958_MAN_WP                      0x157c
#define AIU_MEM_IEC958_MAN_RP                      0x157d
#define AIU_MEM_IEC958_LEVEL                       0x157e
#define AIU_MEM_IEC958_BUF_CNTL                    0x157f
#define AIU_AIFIFO_CTRL                            0x1580
#define AIU_AIFIFO_STATUS                          0x1581
#define AIU_AIFIFO_GBIT                            0x1582
#define AIU_AIFIFO_CLB                             0x1583
#define AIU_MEM_AIFIFO_START_PTR                   0x1584
#define AIU_MEM_AIFIFO_CURR_PTR                    0x1585
#define AIU_MEM_AIFIFO_END_PTR                     0x1586
#define AIU_MEM_AIFIFO_BYTES_AVAIL                 0x1587
#define AIU_MEM_AIFIFO_CONTROL                     0x1588
#define AIU_MEM_AIFIFO_MAN_WP                      0x1589
#define AIU_MEM_AIFIFO_MAN_RP                      0x158a
#define AIU_MEM_AIFIFO_LEVEL                       0x158b
#define AIU_MEM_AIFIFO_BUF_CNTL                    0x158c
#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT              0x158d
#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT             0x158e
#define AIU_MEM_AIFIFO_MEM_CTL                     0x158f
#define AIFIFO_TIME_STAMP_CNTL                     0x1590
#define AIFIFO_TIME_STAMP_SYNC_0                   0x1591
#define AIFIFO_TIME_STAMP_SYNC_1                   0x1592
#define AIFIFO_TIME_STAMP_0                        0x1593
#define AIFIFO_TIME_STAMP_1                        0x1594
#define AIFIFO_TIME_STAMP_2                        0x1595
#define AIFIFO_TIME_STAMP_3                        0x1596
#define AIFIFO_TIME_STAMP_LENGTH                   0x1597
#define AIFIFO2_TIME_STAMP_CNTL                    0x1598
#define AIFIFO2_TIME_STAMP_SYNC_0                  0x1599
#define AIFIFO2_TIME_STAMP_SYNC_1                  0x159a
#define AIFIFO2_TIME_STAMP_0                       0x159b
#define AIFIFO2_TIME_STAMP_1                       0x159c
#define AIFIFO2_TIME_STAMP_2                       0x159d
#define AIFIFO2_TIME_STAMP_3                       0x159e
#define AIFIFO2_TIME_STAMP_LENGTH                  0x159f
#define IEC958_TIME_STAMP_CNTL                     0x15a0
#define IEC958_TIME_STAMP_SYNC_0                   0x15a1
#define IEC958_TIME_STAMP_SYNC_1                   0x15a2
#define IEC958_TIME_STAMP_0                        0x15a3
#define IEC958_TIME_STAMP_1                        0x15a4
#define IEC958_TIME_STAMP_2                        0x15a5
#define IEC958_TIME_STAMP_3                        0x15a6
#define IEC958_TIME_STAMP_LENGTH                   0x15a7
#define AIU_MEM_AIFIFO2_MEM_CTL                    0x15a8
#define AIU_I2S_CBUS_DDR_CNTL                      0x15a9
#define AIU_I2S_CBUS_DDR_WDATA                     0x15aa
#define AIU_I2S_CBUS_DDR_ADDR                      0x15ab
#define AIADR                                      0x1738
#define AICSR                                      0x1739
#define AIDAT                                      0x173a
#define AIGBIT                                     0x173b
#define AICLB                                      0x173c
#define HD0                                        0x1780
#define HD1                                        0x1781
#define SHD0                                       0x1782
#define SHD1                                       0x1783
#define SYND                                       0x1784
#define ECDCT                                      0x1785
#define ECDSTAT                                    0x1786
#define CTR0                                       0x1787
#define CTR1                                       0x1788
#define CTR2                                       0x1789
#define STAT0                                      0x178a
#define INT                                        0x178b
#define TCTR0                                      0x178c
#define TSTAT0                                     0x178d
#define TSTAT1                                     0x178e
#define VPP_DUMMY_DATA                             0x1d00
#define VPP_LINE_IN_LENGTH                         0x1d01
#define VPP_PIC_IN_HEIGHT                          0x1d02
#define VPP_SCALE_COEF_IDX                         0x1d03
#define VPP_SCALE_COEF                             0x1d04
#define VPP_VSC_REGION12_STARTP                    0x1d05
#define VPP_VSC_REGION34_STARTP                    0x1d06
#define VPP_VSC_REGION4_ENDP                       0x1d07
#define VPP_VSC_START_PHASE_STEP                   0x1d08
#define VPP_VSC_REGION0_PHASE_SLOPE                0x1d09
#define VPP_VSC_REGION1_PHASE_SLOPE                0x1d0a
#define VPP_VSC_REGION3_PHASE_SLOPE                0x1d0b
#define VPP_VSC_REGION4_PHASE_SLOPE                0x1d0c
#define VPP_VSC_PHASE_CTRL                         0x1d0d
#define VPP_VSC_INI_PHASE                          0x1d0e
#define VPP_HSC_REGION12_STARTP                    0x1d10
#define VPP_HSC_REGION34_STARTP                    0x1d11
#define VPP_HSC_REGION4_ENDP                       0x1d12
#define VPP_HSC_START_PHASE_STEP                   0x1d13
#define VPP_HSC_REGION0_PHASE_SLOPE                0x1d14
#define VPP_HSC_REGION1_PHASE_SLOPE                0x1d15
#define VPP_HSC_REGION3_PHASE_SLOPE                0x1d16
#define VPP_HSC_REGION4_PHASE_SLOPE                0x1d17
#define VPP_HSC_PHASE_CTRL                         0x1d18
#define VPP_SC_MISC                                0x1d19
#define VPP_PREBLEND_VD1_H_START_END               0x1d1a
#define VPP_PREBLEND_VD1_V_START_END               0x1d1b
#define VPP_POSTBLEND_VD1_H_START_END              0x1d1c
#define VPP_POSTBLEND_VD1_V_START_END              0x1d1d
#define VPP_BLEND_VD2_H_START_END                  0x1d1e
#define VPP_BLEND_VD2_V_START_END                  0x1d1f
#define VPP_PREBLEND_H_SIZE                        0x1d20
#define VPP_POSTBLEND_H_SIZE                       0x1d21
#define VPP_HOLD_LINES                             0x1d22
#define VPP_BLEND_ONECOLOR_CTRL                    0x1d23
#define VPP_PREBLEND_CURRENT_XY                    0x1d24
#define VPP_POSTBLEND_CURRENT_XY                   0x1d25
#define VPP_MISC                                   0x1d26
#define VPP_OFIFO_SIZE                             0x1d27
#define VPP_FIFO_STATUS                            0x1d28
#define VPP_SMOKE_CTRL                             0x1d29
#define VPP_SMOKE1_VAL                             0x1d2a
#define VPP_SMOKE2_VAL                             0x1d2b
#define VPP_SMOKE3_VAL                             0x1d2c
#define VPP_SMOKE1_H_START_END                     0x1d2d
#define VPP_SMOKE1_V_START_END                     0x1d2e
#define VPP_SMOKE2_H_START_END                     0x1d2f
#define VPP_SMOKE2_V_START_END                     0x1d30
#define VPP_SMOKE3_H_START_END                     0x1d31
#define VPP_SMOKE3_V_START_END                     0x1d32
#define VPP_SCO_FIFO_CTRL                          0x1d33
#define VPP_VADJ_CTRL                              0x1d40
#define VPP_VADJ1_Y                                0x1d41
#define VPP_VADJ1_MA_MB                            0x1d42
#define VPP_VADJ1_MC_MD                            0x1d43
#define VPP_VADJ2_Y                                0x1d44
#define VPP_VADJ2_MA_MB                            0x1d45
#define VPP_VADJ2_MC_MD                            0x1d46
#define VPP_HSHARP_CTRL                            0x1d50
#define VPP_HSHARP_LUMA_THRESH01                   0x1d51
#define VPP_HSHARP_LUMA_THRESH23                   0x1d52
#define VPP_HSHARP_CHROMA_THRESH01                 0x1d53
#define VPP_HSHARP_CHROMA_THRESH23                 0x1d54
#define VPP_HSHARP_LUMA_GAIN                       0x1d55
#define VPP_HSHARP_CHROMA_GAIN                     0x1d56
#define VPP_MATRIX_CTRL                            0x1d5f
#define VPP_MATRIX_COEF00_01                       0x1d60
#define VPP_MATRIX_COEF02_10                       0x1d61
#define VPP_MATRIX_COEF11_12                       0x1d62
#define VPP_MATRIX_COEF20_21                       0x1d63
#define VPP_MATRIX_COEF22                          0x1d64
#define VPP_MATRIX_OFFSET0_1                       0x1d65
#define VPP_MATRIX_OFFSET2                         0x1d66
#define VPP_MATRIX_PRE_OFFSET0_1                   0x1d67
#define VPP_MATRIX_PRE_OFFSET2                     0x1d68
#define VPP_DUMMY_DATA1                            0x1d69
#define VPP_GAINOFF_CTRL0                          0x1d6a
#define VPP_GAINOFF_CTRL1                          0x1d6b
#define VPP_GAINOFF_CTRL2                          0x1d6c
#define VPP_GAINOFF_CTRL3                          0x1d6d
#define VPP_GAINOFF_CTRL4                          0x1d6e
#define VPP_CHROMA_ADDR_PORT                       0x1d70
#define VPP_CHROMA_DATA_PORT                       0x1d71
#define VPP_GCLK_CTRL0                             0x1d72
#define VPP_GCLK_CTRL1                             0x1d73
#define VPP_SC_GCLK_CTRL                           0x1d74
#define VPP_BLACKEXT_CTRL                          0x1d80
#define VPP_DNLP_CTRL_00                           0x1d81
#define VPP_DNLP_CTRL_01                           0x1d82
#define VPP_DNLP_CTRL_02                           0x1d83
#define VPP_DNLP_CTRL_03                           0x1d84
#define VPP_DNLP_CTRL_04                           0x1d85
#define VPP_DNLP_CTRL_05                           0x1d86
#define VPP_DNLP_CTRL_06                           0x1d87
#define VPP_DNLP_CTRL_07                           0x1d88
#define VPP_DNLP_CTRL_08                           0x1d89
#define VPP_DNLP_CTRL_09                           0x1d8a
#define VPP_DNLP_CTRL_10                           0x1d8b
#define VPP_DNLP_CTRL_11                           0x1d8c
#define VPP_DNLP_CTRL_12                           0x1d8d
#define VPP_DNLP_CTRL_13                           0x1d8e
#define VPP_DNLP_CTRL_14                           0x1d8f
#define VPP_DNLP_CTRL_15                           0x1d90
#define VPP_PEAKING_HGAIN                          0x1d91
#define VPP_PEAKING_VGAIN                          0x1d92
#define VPP_PEAKING_NLP_1                          0x1d93
#define VPP_PEAKING_NLP_2                          0x1d94
#define VPP_PEAKING_NLP_3                          0x1d95
#define VPP_PEAKING_NLP_4                          0x1d96
#define VPP_PEAKING_NLP_5                          0x1d97
#define VPP_SHARP_LIMIT                            0x1d98
#define VPP_VLTI_CTRL                              0x1d99
#define VPP_HLTI_CTRL                              0x1d9a
#define VPP_CTI_CTRL                               0x1d9b
#define VPP_BLUE_STRETCH_1                         0x1d9c
#define VPP_BLUE_STRETCH_2                         0x1d9d
#define VPP_BLUE_STRETCH_3                         0x1d9e
#define VPP_CCORING_CTRL                           0x1da0
#define VPP_VE_ENABLE_CTRL                         0x1da1
#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH          0x1da2
#define VPP_VE_DEMO_CENTER_BAR                     0x1da3
#define VPP_VDO_MEAS_CTRL                          0x1da8
#define VPP_VDO_MEAS_VS_COUNT_HI                   0x1da9
#define VPP_VDO_MEAS_VS_COUNT_LO                   0x1daa
#define VPP2_DUMMY_DATA                            0x1900
#define VPP2_LINE_IN_LENGTH                        0x1901
#define VPP2_PIC_IN_HEIGHT                         0x1902
#define VPP2_SCALE_COEF_IDX                        0x1903
#define VPP2_SCALE_COEF                            0x1904
#define VPP2_VSC_REGION12_STARTP                   0x1905
#define VPP2_VSC_REGION34_STARTP                   0x1906
#define VPP2_VSC_REGION4_ENDP                      0x1907
#define VPP2_VSC_START_PHASE_STEP                  0x1908
#define VPP2_VSC_REGION0_PHASE_SLOPE               0x1909
#define VPP2_VSC_REGION1_PHASE_SLOPE               0x190a
#define VPP2_VSC_REGION3_PHASE_SLOPE               0x190b
#define VPP2_VSC_REGION4_PHASE_SLOPE               0x190c
#define VPP2_VSC_PHASE_CTRL                        0x190d
#define VPP2_VSC_INI_PHASE                         0x190e
#define VPP2_HSC_REGION12_STARTP                   0x1910
#define VPP2_HSC_REGION34_STARTP                   0x1911
#define VPP2_HSC_REGION4_ENDP                      0x1912
#define VPP2_HSC_START_PHASE_STEP                  0x1913
#define VPP2_HSC_REGION0_PHASE_SLOPE               0x1914
#define VPP2_HSC_REGION1_PHASE_SLOPE               0x1915
#define VPP2_HSC_REGION3_PHASE_SLOPE               0x1916
#define VPP2_HSC_REGION4_PHASE_SLOPE               0x1917
#define VPP2_HSC_PHASE_CTRL                        0x1918
#define VPP2_SC_MISC                               0x1919
#define VPP2_PREBLEND_VD1_H_START_END              0x191a
#define VPP2_PREBLEND_VD1_V_START_END              0x191b
#define VPP2_POSTBLEND_VD1_H_START_END             0x191c
#define VPP2_POSTBLEND_VD1_V_START_END             0x191d
#define VPP2_PREBLEND_H_SIZE                       0x1920
#define VPP2_POSTBLEND_H_SIZE                      0x1921
#define VPP2_HOLD_LINES                            0x1922
#define VPP2_BLEND_ONECOLOR_CTRL                   0x1923
#define VPP2_PREBLEND_CURRENT_XY                   0x1924
#define VPP2_POSTBLEND_CURRENT_XY                  0x1925
#define VPP2_MISC                                  0x1926
#define VPP2_OFIFO_SIZE                            0x1927
#define VPP2_FIFO_STATUS                           0x1928
#define VPP2_SMOKE_CTRL                            0x1929
#define VPP2_SMOKE1_VAL                            0x192a
#define VPP2_SMOKE2_VAL                            0x192b
#define VPP2_SMOKE1_H_START_END                    0x192d
#define VPP2_SMOKE1_V_START_END                    0x192e
#define VPP2_SMOKE2_H_START_END                    0x192f
#define VPP2_SMOKE2_V_START_END                    0x1930
#define VPP2_SCO_FIFO_CTRL                         0x1933
#define VPP2_VADJ_CTRL                             0x1940
#define VPP2_VADJ1_Y                               0x1941
#define VPP2_VADJ1_MA_MB                           0x1942
#define VPP2_VADJ1_MC_MD                           0x1943
#define VPP2_VADJ2_Y                               0x1944
#define VPP2_VADJ2_MA_MB                           0x1945
#define VPP2_VADJ2_MC_MD                           0x1946
#define VPP2_HSHARP_CTRL                           0x1950
#define VPP2_HSHARP_LUMA_THRESH01                  0x1951
#define VPP2_HSHARP_LUMA_THRESH23                  0x1952
#define VPP2_HSHARP_CHROMA_THRESH01                0x1953
#define VPP2_HSHARP_CHROMA_THRESH23                0x1954
#define VPP2_HSHARP_LUMA_GAIN                      0x1955
#define VPP2_HSHARP_CHROMA_GAIN                    0x1956
#define VPP2_MATRIX_CTRL                           0x195f
#define VPP2_MATRIX_COEF00_01                      0x1960
#define VPP2_MATRIX_COEF02_10                      0x1961
#define VPP2_MATRIX_COEF11_12                      0x1962
#define VPP2_MATRIX_COEF20_21                      0x1963
#define VPP2_MATRIX_COEF22                         0x1964
#define VPP2_MATRIX_OFFSET0_1                      0x1965
#define VPP2_MATRIX_OFFSET2                        0x1966
#define VPP2_MATRIX_PRE_OFFSET0_1                  0x1967
#define VPP2_MATRIX_PRE_OFFSET2                    0x1968
#define VPP2_DUMMY_DATA1                           0x1969
#define VPP2_GAINOFF_CTRL0                         0x196a
#define VPP2_GAINOFF_CTRL1                         0x196b
#define VPP2_GAINOFF_CTRL2                         0x196c
#define VPP2_GAINOFF_CTRL3                         0x196d
#define VPP2_GAINOFF_CTRL4                         0x196e
#define VPP2_CHROMA_ADDR_PORT                      0x1970
#define VPP2_CHROMA_DATA_PORT                      0x1971
#define VPP2_GCLK_CTRL0                            0x1972
#define VPP2_GCLK_CTRL1                            0x1973
#define VPP2_SC_GCLK_CTRL                          0x1974
#define VPP2_BLACKEXT_CTRL                         0x1980
#define VPP2_DNLP_CTRL_00                          0x1981
#define VPP2_DNLP_CTRL_01                          0x1982
#define VPP2_DNLP_CTRL_02                          0x1983
#define VPP2_DNLP_CTRL_03                          0x1984
#define VPP2_DNLP_CTRL_04                          0x1985
#define VPP2_DNLP_CTRL_05                          0x1986
#define VPP2_DNLP_CTRL_06                          0x1987
#define VPP2_DNLP_CTRL_07                          0x1988
#define VPP2_DNLP_CTRL_08                          0x1989
#define VPP2_DNLP_CTRL_09                          0x198a
#define VPP2_DNLP_CTRL_10                          0x198b
#define VPP2_DNLP_CTRL_11                          0x198c
#define VPP2_DNLP_CTRL_12                          0x198d
#define VPP2_DNLP_CTRL_13                          0x198e
#define VPP2_DNLP_CTRL_14                          0x198f
#define VPP2_DNLP_CTRL_15                          0x1990
#define VPP2_PEAKING_HGAIN                         0x1991
#define VPP2_PEAKING_VGAIN                         0x1992
#define VPP2_PEAKING_NLP_1                         0x1993
#define VPP2_PEAKING_NLP_2                         0x1994
#define VPP2_PEAKING_NLP_3                         0x1995
#define VPP2_PEAKING_NLP_4                         0x1996
#define VPP2_PEAKING_NLP_5                         0x1997
#define VPP2_SHARP_LIMIT                           0x1998
#define VPP2_VLTI_CTRL                             0x1999
#define VPP2_HLTI_CTRL                             0x199a
#define VPP2_CTI_CTRL                              0x199b
#define VPP2_BLUE_STRETCH_1                        0x199c
#define VPP2_BLUE_STRETCH_2                        0x199d
#define VPP2_BLUE_STRETCH_3                        0x199e
#define VPP2_CCORING_CTRL                          0x19a0
#define VPP2_VE_ENABLE_CTRL                        0x19a1
#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH         0x19a2
#define VPP2_VE_DEMO_CENTER_BAR                    0x19a3
#define VPP2_VDO_MEAS_CTRL                         0x19a8
#define VPP2_VDO_MEAS_VS_COUNT_HI                  0x19a9
#define VPP2_VDO_MEAS_VS_COUNT_LO                  0x19aa
#define GE2D_GEN_CTRL0                             0x18a0
#define GE2D_GEN_CTRL1                             0x18a1
#define GE2D_GEN_CTRL2                             0x18a2
#define GE2D_CMD_CTRL                              0x18a3
#define GE2D_STATUS0                               0x18a4
#define GE2D_STATUS1                               0x18a5
#define GE2D_SRC1_DEF_COLOR                        0x18a6
#define GE2D_SRC1_CLIPX_START_END                  0x18a7
#define GE2D_SRC1_CLIPY_START_END                  0x18a8
#define GE2D_SRC1_CANVAS                           0x18a9
#define GE2D_SRC1_X_START_END                      0x18aa
#define GE2D_SRC1_Y_START_END                      0x18ab
#define GE2D_SRC1_LUT_ADDR                         0x18ac
#define GE2D_SRC1_LUT_DAT                          0x18ad
#define GE2D_SRC1_FMT_CTRL                         0x18ae
#define GE2D_SRC2_DEF_COLOR                        0x18af
#define GE2D_SRC2_CLIPX_START_END                  0x18b0
#define GE2D_SRC2_CLIPY_START_END                  0x18b1
#define GE2D_SRC2_X_START_END                      0x18b2
#define GE2D_SRC2_Y_START_END                      0x18b3
#define GE2D_DST_CLIPX_START_END                   0x18b4
#define GE2D_DST_CLIPY_START_END                   0x18b5
#define GE2D_DST_X_START_END                       0x18b6
#define GE2D_DST_Y_START_END                       0x18b7
#define GE2D_SRC2_DST_CANVAS                       0x18b8
#define GE2D_VSC_START_PHASE_STEP                  0x18b9
#define GE2D_VSC_PHASE_SLOPE                       0x18ba
#define GE2D_VSC_INI_CTRL                          0x18bb
#define GE2D_HSC_START_PHASE_STEP                  0x18bc
#define GE2D_HSC_PHASE_SLOPE                       0x18bd
#define GE2D_HSC_INI_CTRL                          0x18be
#define GE2D_HSC_ADV_CTRL                          0x18bf
#define GE2D_SC_MISC_CTRL                          0x18c0
#define GE2D_VSC_NRND_POINT                        0x18c1
#define GE2D_VSC_NRND_PHASE                        0x18c2
#define GE2D_HSC_NRND_POINT                        0x18c3
#define GE2D_HSC_NRND_PHASE                        0x18c4
#define GE2D_MATRIX_PRE_OFFSET                     0x18c5
#define GE2D_MATRIX_COEF00_01                      0x18c6
#define GE2D_MATRIX_COEF02_10                      0x18c7
#define GE2D_MATRIX_COEF11_12                      0x18c8
#define GE2D_MATRIX_COEF20_21                      0x18c9
#define GE2D_MATRIX_COEF22_CTRL                    0x18ca
#define GE2D_MATRIX_OFFSET                         0x18cb
#define GE2D_ALU_OP_CTRL                           0x18cc
#define GE2D_ALU_CONST_COLOR                       0x18cd
#define GE2D_SRC1_KEY                              0x18ce
#define GE2D_SRC1_KEY_MASK                         0x18cf
#define GE2D_SRC2_KEY                              0x18d0
#define GE2D_SRC2_KEY_MASK                         0x18d1
#define GE2D_DST_BITMASK                           0x18d2
#define GE2D_DP_ONOFF_CTRL                         0x18d3
#define GE2D_SCALE_COEF_IDX                        0x18d4
#define GE2D_SCALE_COEF                            0x18d5
#define GE2D_SRC_OUTSIDE_ALPHA                     0x18d6
#define GE2D_ANTIFLICK_CTRL0                       0x18d8
#define GE2D_ANTIFLICK_CTRL1                       0x18d9
#define GE2D_ANTIFLICK_COLOR_FILT0                 0x18da
#define GE2D_ANTIFLICK_COLOR_FILT1                 0x18db
#define GE2D_ANTIFLICK_COLOR_FILT2                 0x18dc
#define GE2D_ANTIFLICK_COLOR_FILT3                 0x18dd
#define GE2D_ANTIFLICK_ALPHA_FILT0                 0x18de
#define GE2D_ANTIFLICK_ALPHA_FILT1                 0x18df
#define GE2D_ANTIFLICK_ALPHA_FILT2                 0x18e0
#define GE2D_ANTIFLICK_ALPHA_FILT3                 0x18e1
#define GE2D_SRC1_RANGE_MAP_Y_CTRL                 0x18e3
#define GE2D_SRC1_RANGE_MAP_CB_CTRL                0x18e4
#define GE2D_SRC1_RANGE_MAP_CR_CTRL                0x18e5
#define GE2D_ARB_BURST_NUM                         0x18e6
#define GE2D_TID_TOKEN                             0x18e7
#define GE2D_GEN_CTRL3                             0x18e8
#define GE2D_STATUS2                               0x18e9
#define CSI2_CLK_RESET                             0x2a00
#define CSI2_GEN_CTRL0                             0x2a01
#define CSI2_FORCE_PIC_SIZE                        0x2a02
#define CSI2_DDR_START_ADDR                        0x2a03
#define CSI2_DDR_END_ADDR                          0x2a04
#define CSI2_INTERRUPT_CTRL_STAT                   0x2a05
#define CSI2_PIC_SIZE_STAT                         0x2a06
#define CSI2_GEN_STAT0                             0x2a07
#define CSI2_DDR_WRPT_STAT                         0x2a08
#define CSI2_FS_EMBED_DDR_START                    0x2a09
#define CSI2_FS_EMBED_DDR_END                      0x2a0a
#define CSI2_FE_EMBED_DDR_START                    0x2a0b
#define CSI2_FE_EMBED_DDR_END                      0x2a0c
#define CSI2_MEM_PIXEL_BYTE_CNT                    0x2a0d
#define CSI2_MEM_PIXEL_LINE_CNT                    0x2a0e
#define CSI2_PIXEL_DDR_START                       0x2a0f
#define CSI2_PIXEL_DDR_END                         0x2a10
#define CSI2_USER_DDR_START                        0x2a11
#define CSI2_USER_DDR_END                          0x2a12
#define CSI2_DATA_TYPE_IN_MEM                      0x2a13
#define CSI2_ERR_STAT0                             0x2a14
#define VIU_ADDR_START                             0x1a00
#define VIU_ADDR_END                               0x1aff
#define TRACE_REG                                  0x1a08
#define VIU_SW_RESET                               0x1a01
#define VIU_OSD1_CTRL_STAT                         0x1a10
#define VIU_OSD1_CTRL_STAT2                        0x1a2d
#define VIU_OSD1_COLOR_ADDR                        0x1a11
#define VIU_OSD1_COLOR                             0x1a12
#define VIU_OSD1_TCOLOR_AG0                        0x1a17
#define VIU_OSD1_TCOLOR_AG1                        0x1a18
#define VIU_OSD1_TCOLOR_AG2                        0x1a19
#define VIU_OSD1_TCOLOR_AG3                        0x1a1a
#define VIU_OSD1_BLK0_CFG_W0                       0x1a1b
#define VIU_OSD1_BLK1_CFG_W0                       0x1a1f
#define VIU_OSD1_BLK2_CFG_W0                       0x1a23
#define VIU_OSD1_BLK3_CFG_W0                       0x1a27
#define VIU_OSD1_BLK0_CFG_W1                       0x1a1c
#define VIU_OSD1_BLK1_CFG_W1                       0x1a20
#define VIU_OSD1_BLK2_CFG_W1                       0x1a24
#define VIU_OSD1_BLK3_CFG_W1                       0x1a28
#define VIU_OSD1_BLK0_CFG_W2                       0x1a1d
#define VIU_OSD1_BLK1_CFG_W2                       0x1a21
#define VIU_OSD1_BLK2_CFG_W2                       0x1a25
#define VIU_OSD1_BLK3_CFG_W2                       0x1a29
#define VIU_OSD1_BLK0_CFG_W3                       0x1a1e
#define VIU_OSD1_BLK1_CFG_W3                       0x1a22
#define VIU_OSD1_BLK2_CFG_W3                       0x1a26
#define VIU_OSD1_BLK3_CFG_W3                       0x1a2a
#define VIU_OSD1_BLK0_CFG_W4                       0x1a13
#define VIU_OSD1_BLK1_CFG_W4                       0x1a14
#define VIU_OSD1_BLK2_CFG_W4                       0x1a15
#define VIU_OSD1_BLK3_CFG_W4                       0x1a16
#define VIU_OSD1_FIFO_CTRL_STAT                    0x1a2b
#define VIU_OSD1_TEST_RDDATA                       0x1a2c
#define VIU_OSD2_CTRL_STAT                         0x1a30
#define VIU_OSD2_CTRL_STAT2                        0x1a4d
#define VIU_OSD2_COLOR_ADDR                        0x1a31
#define VIU_OSD2_COLOR                             0x1a32
#define VIU_OSD2_HL1_H_START_END                   0x1a33
#define VIU_OSD2_HL1_V_START_END                   0x1a34
#define VIU_OSD2_HL2_H_START_END                   0x1a35
#define VIU_OSD2_HL2_V_START_END                   0x1a36
#define VIU_OSD2_TCOLOR_AG0                        0x1a37
#define VIU_OSD2_TCOLOR_AG1                        0x1a38
#define VIU_OSD2_TCOLOR_AG2                        0x1a39
#define VIU_OSD2_TCOLOR_AG3                        0x1a3a
#define VIU_OSD2_BLK0_CFG_W0                       0x1a3b
#define VIU_OSD2_BLK1_CFG_W0                       0x1a3f
#define VIU_OSD2_BLK2_CFG_W0                       0x1a43
#define VIU_OSD2_BLK3_CFG_W0                       0x1a47
#define VIU_OSD2_BLK0_CFG_W1                       0x1a3c
#define VIU_OSD2_BLK1_CFG_W1                       0x1a40
#define VIU_OSD2_BLK2_CFG_W1                       0x1a44
#define VIU_OSD2_BLK3_CFG_W1                       0x1a48
#define VIU_OSD2_BLK0_CFG_W2                       0x1a3d
#define VIU_OSD2_BLK1_CFG_W2                       0x1a41
#define VIU_OSD2_BLK2_CFG_W2                       0x1a45
#define VIU_OSD2_BLK3_CFG_W2                       0x1a49
#define VIU_OSD2_BLK0_CFG_W3                       0x1a3e
#define VIU_OSD2_BLK1_CFG_W3                       0x1a42
#define VIU_OSD2_BLK2_CFG_W3                       0x1a46
#define VIU_OSD2_BLK3_CFG_W3                       0x1a4a
#define VIU_OSD2_BLK0_CFG_W4                       0x1a64
#define VIU_OSD2_BLK1_CFG_W4                       0x1a65
#define VIU_OSD2_BLK2_CFG_W4                       0x1a66
#define VIU_OSD2_BLK3_CFG_W4                       0x1a67
#define VIU_OSD2_FIFO_CTRL_STAT                    0x1a4b
#define VIU_OSD2_TEST_RDDATA                       0x1a4c
#define VD1_IF0_GEN_REG                            0x1a50
#define VD1_IF0_CANVAS0                            0x1a51
#define VD1_IF0_CANVAS1                            0x1a52
#define VD1_IF0_LUMA_X0                            0x1a53
#define VD1_IF0_LUMA_Y0                            0x1a54
#define VD1_IF0_CHROMA_X0                          0x1a55
#define VD1_IF0_CHROMA_Y0                          0x1a56
#define VD1_IF0_LUMA_X1                            0x1a57
#define VD1_IF0_LUMA_Y1                            0x1a58
#define VD1_IF0_CHROMA_X1                          0x1a59
#define VD1_IF0_CHROMA_Y1                          0x1a5a
#define VD1_IF0_RPT_LOOP                           0x1a5b
#define VD1_IF0_LUMA0_RPT_PAT                      0x1a5c
#define VD1_IF0_CHROMA0_RPT_PAT                    0x1a5d
#define VD1_IF0_LUMA1_RPT_PAT                      0x1a5e
#define VD1_IF0_CHROMA1_RPT_PAT                    0x1a5f
#define VD1_IF0_LUMA_PSEL                          0x1a60
#define VD1_IF0_CHROMA_PSEL                        0x1a61
#define VD1_IF0_DUMMY_PIXEL                        0x1a62
#define VD1_IF0_LUMA_FIFO_SIZE                     0x1a63
#define VD1_IF0_RANGE_MAP_Y                        0x1a6a
#define VD1_IF0_RANGE_MAP_CB                       0x1a6b
#define VD1_IF0_RANGE_MAP_CR                       0x1a6c
#define VD1_IF0_GEN_REG2                           0x1a6d
#define VIU_VD1_FMT_CTRL                           0x1a68
#define VIU_VD1_FMT_W                              0x1a69
#define VD2_IF0_GEN_REG                            0x1a70
#define VD2_IF0_CANVAS0                            0x1a71
#define VD2_IF0_CANVAS1                            0x1a72
#define VD2_IF0_LUMA_X0                            0x1a73
#define VD2_IF0_LUMA_Y0                            0x1a74
#define VD2_IF0_CHROMA_X0                          0x1a75
#define VD2_IF0_CHROMA_Y0                          0x1a76
#define VD2_IF0_LUMA_X1                            0x1a77
#define VD2_IF0_LUMA_Y1                            0x1a78
#define VD2_IF0_CHROMA_X1                          0x1a79
#define VD2_IF0_CHROMA_Y1                          0x1a7a
#define VD2_IF0_RPT_LOOP                           0x1a7b
#define VD2_IF0_LUMA0_RPT_PAT                      0x1a7c
#define VD2_IF0_CHROMA0_RPT_PAT                    0x1a7d
#define VD2_IF0_LUMA1_RPT_PAT                      0x1a7e
#define VD2_IF0_CHROMA1_RPT_PAT                    0x1a7f
#define VD2_IF0_LUMA_PSEL                          0x1a80
#define VD2_IF0_CHROMA_PSEL                        0x1a81
#define VD2_IF0_DUMMY_PIXEL                        0x1a82
#define VD2_IF0_LUMA_FIFO_SIZE                     0x1a83
#define VD2_IF0_RANGE_MAP_Y                        0x1a8a
#define VD2_IF0_RANGE_MAP_CB                       0x1a8b
#define VD2_IF0_RANGE_MAP_CR                       0x1a8c
#define VD2_IF0_GEN_REG2                           0x1a8d
#define VIU_VD2_FMT_CTRL                           0x1a88
#define VIU_VD2_FMT_W                              0x1a89
#define DI_PRE_CTRL                                0x1700
#define DI_POST_CTRL                               0x1701
#define DI_POST_SIZE                               0x1702
#define DI_PRE_SIZE                                0x1703
#define DI_EI_CTRL0                                0x1704
#define DI_EI_CTRL1                                0x1705
#define DI_EI_CTRL2                                0x1706
#define DI_NR_CTRL0                                0x1707
#define DI_NR_CTRL1                                0x1708
#define DI_NR_CTRL2                                0x1709
#define DI_NR_CTRL3                                0x170a
#define DI_MTN_CTRL                                0x170b
#define DI_MTN_CTRL1                               0x170c
#define DI_BLEND_CTRL                              0x170d
#define DI_BLEND_CTRL1                             0x170e
#define DI_BLEND_CTRL2                             0x170f
#define DI_BLEND_REG0_X                            0x1710
#define DI_BLEND_REG0_Y                            0x1711
#define DI_BLEND_REG1_X                            0x1712
#define DI_BLEND_REG1_Y                            0x1713
#define DI_BLEND_REG2_X                            0x1714
#define DI_BLEND_REG2_Y                            0x1715
#define DI_BLEND_REG3_X                            0x1716
#define DI_BLEND_REG3_Y                            0x1717
#define DI_CLKG_CTRL                               0x1718
#define DI_MC_REG0_X                               0x1720
#define DI_MC_REG0_Y                               0x1721
#define DI_MC_REG1_X                               0x1722
#define DI_MC_REG1_Y                               0x1723
#define DI_MC_REG2_X                               0x1724
#define DI_MC_REG2_Y                               0x1725
#define DI_MC_REG3_X                               0x1726
#define DI_MC_REG3_Y                               0x1727
#define DI_MC_REG4_X                               0x1728
#define DI_MC_REG4_Y                               0x1729
#define DI_MC_32LVL0                               0x172a
#define DI_MC_32LVL1                               0x172b
#define DI_MC_22LVL0                               0x172c
#define DI_MC_22LVL1                               0x172d
#define DI_MC_22LVL2                               0x172e
#define DI_MC_CTRL                                 0x172f
#define DI_INTR_CTRL                               0x1730
#define DI_INFO_ADDR                               0x1731
#define DI_INFO_DATA                               0x1732
#define DI_PRE_HOLD                                0x1733
#define DI_NRWR_X                                  0x17c0
#define DI_NRWR_Y                                  0x17c1
#define DI_NRWR_CTRL                               0x17c2
#define DI_MTNWR_X                                 0x17c3
#define DI_MTNWR_Y                                 0x17c4
#define DI_MTNWR_CTRL                              0x17c5
#define DI_DIWR_X                                  0x17c6
#define DI_DIWR_Y                                  0x17c7
#define DI_DIWR_CTRL                               0x17c8
#define DI_MTNCRD_X                                0x17c9
#define DI_MTNCRD_Y                                0x17ca
#define DI_MTNPRD_X                                0x17cb
#define DI_MTNPRD_Y                                0x17cc
#define DI_MTNRD_CTRL                              0x17cd
#define DI_INP_GEN_REG                             0x17ce
#define DI_INP_CANVAS0                             0x17cf
#define DI_INP_LUMA_X0                             0x17d0
#define DI_INP_LUMA_Y0                             0x17d1
#define DI_INP_CHROMA_X0                           0x17d2
#define DI_INP_CHROMA_Y0                           0x17d3
#define DI_INP_RPT_LOOP                            0x17d4
#define DI_INP_LUMA0_RPT_PAT                       0x17d5
#define DI_INP_CHROMA0_RPT_PAT                     0x17d6
#define DI_INP_DUMMY_PIXEL                         0x17d7
#define DI_INP_LUMA_FIFO_SIZE                      0x17d8
#define DI_INP_RANGE_MAP_Y                         0x17ba
#define DI_INP_RANGE_MAP_CB                        0x17bb
#define DI_INP_RANGE_MAP_CR                        0x17bc
#define DI_INP_GEN_REG2                            0x1791
#define DI_INP_FMT_CTRL                            0x17d9
#define DI_INP_FMT_W                               0x17da
#define DI_MEM_GEN_REG                             0x17db
#define DI_MEM_CANVAS0                             0x17dc
#define DI_MEM_LUMA_X0                             0x17dd
#define DI_MEM_LUMA_Y0                             0x17de
#define DI_MEM_CHROMA_X0                           0x17df
#define DI_MEM_CHROMA_Y0                           0x17e0
#define DI_MEM_RPT_LOOP                            0x17e1
#define DI_MEM_LUMA0_RPT_PAT                       0x17e2
#define DI_MEM_CHROMA0_RPT_PAT                     0x17e3
#define DI_MEM_DUMMY_PIXEL                         0x17e4
#define DI_MEM_LUMA_FIFO_SIZE                      0x17e5
#define DI_MEM_RANGE_MAP_Y                         0x17bd
#define DI_MEM_RANGE_MAP_CB                        0x17be
#define DI_MEM_RANGE_MAP_CR                        0x17bf
#define DI_MEM_GEN_REG2                            0x1792
#define DI_MEM_FMT_CTRL                            0x17e6
#define DI_MEM_FMT_W                               0x17e7
#define DI_IF1_GEN_REG                             0x17e8
#define DI_IF1_CANVAS0                             0x17e9
#define DI_IF1_LUMA_X0                             0x17ea
#define DI_IF1_LUMA_Y0                             0x17eb
#define DI_IF1_CHROMA_X0                           0x17ec
#define DI_IF1_CHROMA_Y0                           0x17ed
#define DI_IF1_RPT_LOOP                            0x17ee
#define DI_IF1_LUMA0_RPT_PAT                       0x17ef
#define DI_IF1_CHROMA0_RPT_PAT                     0x17f0
#define DI_IF1_DUMMY_PIXEL                         0x17f1
#define DI_IF1_LUMA_FIFO_SIZE                      0x17f2
#define DI_IF1_RANGE_MAP_Y                         0x17fc
#define DI_IF1_RANGE_MAP_CB                        0x17fd
#define DI_IF1_RANGE_MAP_CR                        0x17fe
#define DI_IF1_GEN_REG2                            0x1790
#define DI_IF1_FMT_CTRL                            0x17f3
#define DI_IF1_FMT_W                               0x17f4
#define DI_CHAN2_GEN_REG                           0x17f5
#define DI_CHAN2_CANVAS                            0x17f6
#define DI_CHAN2_LUMA_X                            0x17f7
#define DI_CHAN2_LUMA_Y                            0x17f8
#define DI_CHAN2_RPT_LOOP                          0x17f9
#define DI_CHAN2_LUMA_RPT_PAT                      0x17fa
#define DI_CHAN2_DUMMY_PIXEL                       0x17fb
#define DI_CHAN2_RANGE_MAP_Y                       0x17b9
#define VIU2_ADDR_START                            0x1e00
#define VIU2_ADDR_END                              0x1eff
#define VIU2_OSD1_CTRL_STAT                        0x1e10
#define VIU2_OSD1_CTRL_STAT2                       0x1e2d
#define VIU2_OSD1_COLOR_ADDR                       0x1e11
#define VIU2_OSD1_COLOR                            0x1e12
#define VIU2_OSD1_TCOLOR_AG0                       0x1e17
#define VIU2_OSD1_TCOLOR_AG1                       0x1e18
#define VIU2_OSD1_TCOLOR_AG2                       0x1e19
#define VIU2_OSD1_TCOLOR_AG3                       0x1e1a
#define VIU2_OSD1_BLK0_CFG_W0                      0x1e1b
#define VIU2_OSD1_BLK1_CFG_W0                      0x1e1f
#define VIU2_OSD1_BLK2_CFG_W0                      0x1e23
#define VIU2_OSD1_BLK3_CFG_W0                      0x1e27
#define VIU2_OSD1_BLK0_CFG_W1                      0x1e1c
#define VIU2_OSD1_BLK1_CFG_W1                      0x1e20
#define VIU2_OSD1_BLK2_CFG_W1                      0x1e24
#define VIU2_OSD1_BLK3_CFG_W1                      0x1e28
#define VIU2_OSD1_BLK0_CFG_W2                      0x1e1d
#define VIU2_OSD1_BLK1_CFG_W2                      0x1e21
#define VIU2_OSD1_BLK2_CFG_W2                      0x1e25
#define VIU2_OSD1_BLK3_CFG_W2                      0x1e29
#define VIU2_OSD1_BLK0_CFG_W3                      0x1e1e
#define VIU2_OSD1_BLK1_CFG_W3                      0x1e22
#define VIU2_OSD1_BLK2_CFG_W3                      0x1e26
#define VIU2_OSD1_BLK3_CFG_W3                      0x1e2a
#define VIU2_OSD1_BLK0_CFG_W4                      0x1e13
#define VIU2_OSD1_BLK1_CFG_W4                      0x1e14
#define VIU2_OSD1_BLK2_CFG_W4                      0x1e15
#define VIU2_OSD1_BLK3_CFG_W4                      0x1e16
#define VIU2_OSD1_FIFO_CTRL_STAT                   0x1e2b
#define VIU2_OSD1_TEST_RDDATA                      0x1e2c
#define VIU2_OSD2_CTRL_STAT                        0x1e30
#define VIU2_OSD2_CTRL_STAT2                       0x1e4d
#define VIU2_OSD2_COLOR_ADDR                       0x1e31
#define VIU2_OSD2_COLOR                            0x1e32
#define VIU2_OSD2_HL1_H_START_END                  0x1e33
#define VIU2_OSD2_HL1_V_START_END                  0x1e34
#define VIU2_OSD2_HL2_H_START_END                  0x1e35
#define VIU2_OSD2_HL2_V_START_END                  0x1e36
#define VIU2_OSD2_TCOLOR_AG0                       0x1e37
#define VIU2_OSD2_TCOLOR_AG1                       0x1e38
#define VIU2_OSD2_TCOLOR_AG2                       0x1e39
#define VIU2_OSD2_TCOLOR_AG3                       0x1e3a
#define VIU2_OSD2_BLK0_CFG_W0                      0x1e3b
#define VIU2_OSD2_BLK1_CFG_W0                      0x1e3f
#define VIU2_OSD2_BLK2_CFG_W0                      0x1e43
#define VIU2_OSD2_BLK3_CFG_W0                      0x1e47
#define VIU2_OSD2_BLK0_CFG_W1                      0x1e3c
#define VIU2_OSD2_BLK1_CFG_W1                      0x1e40
#define VIU2_OSD2_BLK2_CFG_W1                      0x1e44
#define VIU2_OSD2_BLK3_CFG_W1                      0x1e48
#define VIU2_OSD2_BLK0_CFG_W2                      0x1e3d
#define VIU2_OSD2_BLK1_CFG_W2                      0x1e41
#define VIU2_OSD2_BLK2_CFG_W2                      0x1e45
#define VIU2_OSD2_BLK3_CFG_W2                      0x1e49
#define VIU2_OSD2_BLK0_CFG_W3                      0x1e3e
#define VIU2_OSD2_BLK1_CFG_W3                      0x1e42
#define VIU2_OSD2_BLK2_CFG_W3                      0x1e46
#define VIU2_OSD2_BLK3_CFG_W3                      0x1e4a
#define VIU2_OSD2_BLK0_CFG_W4                      0x1e64
#define VIU2_OSD2_BLK1_CFG_W4                      0x1e65
#define VIU2_OSD2_BLK2_CFG_W4                      0x1e66
#define VIU2_OSD2_BLK3_CFG_W4                      0x1e67
#define VIU2_OSD2_FIFO_CTRL_STAT                   0x1e4b
#define VIU2_OSD2_TEST_RDDATA                      0x1e4c
#define VIU2_VD1_IF0_GEN_REG                       0x1e50
#define VIU2_VD1_IF0_CANVAS0                       0x1e51
#define VIU2_VD1_IF0_CANVAS1                       0x1e52
#define VIU2_VD1_IF0_LUMA_X0                       0x1e53
#define VIU2_VD1_IF0_LUMA_Y0                       0x1e54
#define VIU2_VD1_IF0_CHROMA_X0                     0x1e55
#define VIU2_VD1_IF0_CHROMA_Y0                     0x1e56
#define VIU2_VD1_IF0_LUMA_X1                       0x1e57
#define VIU2_VD1_IF0_LUMA_Y1                       0x1e58
#define VIU2_VD1_IF0_CHROMA_X1                     0x1e59
#define VIU2_VD1_IF0_CHROMA_Y1                     0x1e5a
#define VIU2_VD1_IF0_RPT_LOOP                      0x1e5b
#define VIU2_VD1_IF0_LUMA0_RPT_PAT                 0x1e5c
#define VIU2_VD1_IF0_CHROMA0_RPT_PAT               0x1e5d
#define VIU2_VD1_IF0_LUMA1_RPT_PAT                 0x1e5e
#define VIU2_VD1_IF0_CHROMA1_RPT_PAT               0x1e5f
#define VIU2_VD1_IF0_LUMA_PSEL                     0x1e60
#define VIU2_VD1_IF0_CHROMA_PSEL                   0x1e61
#define VIU2_VD1_IF0_DUMMY_PIXEL                   0x1e62
#define VIU2_VD1_IF0_LUMA_FIFO_SIZE                0x1e63
#define VIU2_VD1_IF0_RANGE_MAP_Y                   0x1e6a
#define VIU2_VD1_IF0_RANGE_MAP_CB                  0x1e6b
#define VIU2_VD1_IF0_RANGE_MAP_CR                  0x1e6c
#define VIU2_VD1_IF0_GEN_REG2                      0x1e6d
#define VIU2_VD1_FMT_CTRL                          0x1e68
#define VIU2_VD1_FMT_W                             0x1e69
#define ENCP_VFIFO2VD_CTL                          0x1b58
#define ENCP_VFIFO2VD_PIXEL_START                  0x1b59
#define ENCP_VFIFO2VD_PIXEL_END                    0x1b5a
#define ENCP_VFIFO2VD_LINE_TOP_START               0x1b5b
#define ENCP_VFIFO2VD_LINE_TOP_END                 0x1b5c
#define ENCP_VFIFO2VD_LINE_BOT_START               0x1b5d
#define ENCP_VFIFO2VD_LINE_BOT_END                 0x1b5e
#define VENC_SYNC_ROUTE                            0x1b60
#define VENC_VIDEO_EXSRC                           0x1b61
#define VENC_DVI_SETTING                           0x1b62
#define VENC_C656_CTRL                             0x1b63
#define VENC_UPSAMPLE_CTRL0                        0x1b64
#define VENC_UPSAMPLE_CTRL1                        0x1b65
#define VENC_UPSAMPLE_CTRL2                        0x1b66
#define TCON_INVERT_CTL                            0x1b67
#define VENC_VIDEO_PROG_MODE                       0x1b68
#define VENC_ENCI_LINE                             0x1b69
#define VENC_ENCI_PIXEL                            0x1b6a
#define VENC_ENCP_LINE                             0x1b6b
#define VENC_ENCP_PIXEL                            0x1b6c
#define VENC_STATA                                 0x1b6d
#define VENC_INTCTRL                               0x1b6e
#define VENC_INTFLAG                               0x1b6f
#define VENC_VIDEO_TST_EN                          0x1b70
#define VENC_VIDEO_TST_MDSEL                       0x1b71
#define VENC_VIDEO_TST_Y                           0x1b72
#define VENC_VIDEO_TST_CB                          0x1b73
#define VENC_VIDEO_TST_CR                          0x1b74
#define VENC_VIDEO_TST_CLRBAR_STRT                 0x1b75
#define VENC_VIDEO_TST_CLRBAR_WIDTH                0x1b76
#define VENC_VIDEO_TST_VDCNT_STSET                 0x1b77
#define VENC_VDAC_DACSEL0                          0x1b78
#define VENC_VDAC_DACSEL1                          0x1b79
#define VENC_VDAC_DACSEL2                          0x1b7a
#define VENC_VDAC_DACSEL3                          0x1b7b
#define VENC_VDAC_DACSEL4                          0x1b7c
#define VENC_VDAC_DACSEL5                          0x1b7d
#define VENC_VDAC_SETTING                          0x1b7e
#define VENC_VDAC_TST_VAL                          0x1b7f
#define VENC_VDAC_DAC0_GAINCTRL                    0x1bf0
#define VENC_VDAC_DAC0_OFFSET                      0x1bf1
#define VENC_VDAC_DAC1_GAINCTRL                    0x1bf2
#define VENC_VDAC_DAC1_OFFSET                      0x1bf3
#define VENC_VDAC_DAC2_GAINCTRL                    0x1bf4
#define VENC_VDAC_DAC2_OFFSET                      0x1bf5
#define VENC_VDAC_DAC3_GAINCTRL                    0x1bf6
#define VENC_VDAC_DAC3_OFFSET                      0x1bf7
#define VENC_VDAC_DAC4_GAINCTRL                    0x1bf8
#define VENC_VDAC_DAC4_OFFSET                      0x1bf9
#define VENC_VDAC_DAC5_GAINCTRL                    0x1bfa
#define VENC_VDAC_DAC5_OFFSET                      0x1bfb
#define VENC_VDAC_FIFO_CTRL                        0x1bfc
#define ENCL_TCON_INVERT_CTL                       0x1bfd
#define ENCP_VIDEO_EN                              0x1b80
#define ENCP_VIDEO_SYNC_MODE                       0x1b81
#define ENCP_MACV_EN                               0x1b82
#define ENCP_VIDEO_Y_SCL                           0x1b83
#define ENCP_VIDEO_PB_SCL                          0x1b84
#define ENCP_VIDEO_PR_SCL                          0x1b85
#define ENCP_VIDEO_SYNC_SCL                        0x1b86
#define ENCP_VIDEO_MACV_SCL                        0x1b87
#define ENCP_VIDEO_Y_OFFST                         0x1b88
#define ENCP_VIDEO_PB_OFFST                        0x1b89
#define ENCP_VIDEO_PR_OFFST                        0x1b8a
#define ENCP_VIDEO_SYNC_OFFST                      0x1b8b
#define ENCP_VIDEO_MACV_OFFST                      0x1b8c
#define ENCP_VIDEO_MODE                            0x1b8d
#define ENCP_VIDEO_MODE_ADV                        0x1b8e
#define ENCP_DBG_PX_RST                            0x1b90
#define ENCP_DBG_LN_RST                            0x1b91
#define ENCP_DBG_PX_INT                            0x1b92
#define ENCP_DBG_LN_INT                            0x1b93
#define ENCP_VIDEO_YFP1_HTIME                      0x1b94
#define ENCP_VIDEO_YFP2_HTIME                      0x1b95
#define ENCP_VIDEO_YC_DLY                          0x1b96
#define ENCP_VIDEO_MAX_PXCNT                       0x1b97
#define ENCP_VIDEO_HSPULS_BEGIN                    0x1b98
#define ENCP_VIDEO_HSPULS_END                      0x1b99
#define ENCP_VIDEO_HSPULS_SWITCH                   0x1b9a
#define ENCP_VIDEO_VSPULS_BEGIN                    0x1b9b
#define ENCP_VIDEO_VSPULS_END                      0x1b9c
#define ENCP_VIDEO_VSPULS_BLINE                    0x1b9d
#define ENCP_VIDEO_VSPULS_ELINE                    0x1b9e
#define ENCP_VIDEO_EQPULS_BEGIN                    0x1b9f
#define ENCP_VIDEO_EQPULS_END                      0x1ba0
#define ENCP_VIDEO_EQPULS_BLINE                    0x1ba1
#define ENCP_VIDEO_EQPULS_ELINE                    0x1ba2
#define ENCP_VIDEO_HAVON_END                       0x1ba3
#define ENCP_VIDEO_HAVON_BEGIN                     0x1ba4
#define ENCP_VIDEO_VAVON_ELINE                     0x1baf
#define ENCP_VIDEO_VAVON_BLINE                     0x1ba6
#define ENCP_VIDEO_HSO_BEGIN                       0x1ba7
#define ENCP_VIDEO_HSO_END                         0x1ba8
#define ENCP_VIDEO_VSO_BEGIN                       0x1ba9
#define ENCP_VIDEO_VSO_END                         0x1baa
#define ENCP_VIDEO_VSO_BLINE                       0x1bab
#define ENCP_VIDEO_VSO_ELINE                       0x1bac
#define ENCP_VIDEO_SYNC_WAVE_CURVE                 0x1bad
#define ENCP_VIDEO_MAX_LNCNT                       0x1bae
#define ENCP_VIDEO_SY_VAL                          0x1bb0
#define ENCP_VIDEO_SY2_VAL                         0x1bb1
#define ENCP_VIDEO_BLANKY_VAL                      0x1bb2
#define ENCP_VIDEO_BLANKPB_VAL                     0x1bb3
#define ENCP_VIDEO_BLANKPR_VAL                     0x1bb4
#define ENCP_VIDEO_HOFFST                          0x1bb5
#define ENCP_VIDEO_VOFFST                          0x1bb6
#define ENCP_VIDEO_RGB_CTRL                        0x1bb7
#define ENCP_VIDEO_FILT_CTRL                       0x1bb8
#define ENCP_VIDEO_OFLD_VPEQ_OFST                  0x1bb9
#define ENCP_VIDEO_OFLD_VOAV_OFST                  0x1bba
#define ENCP_VIDEO_MATRIX_CB                       0x1bbb
#define ENCP_VIDEO_MATRIX_CR                       0x1bbc
#define ENCP_VIDEO_RGBIN_CTRL                      0x1bbd
#define ENCP_MACV_BLANKY_VAL                       0x1bc0
#define ENCP_MACV_MAXY_VAL                         0x1bc1
#define ENCP_MACV_1ST_PSSYNC_STRT                  0x1bc2
#define ENCP_MACV_PSSYNC_STRT                      0x1bc3
#define ENCP_MACV_AGC_STRT                         0x1bc4
#define ENCP_MACV_AGC_END                          0x1bc5
#define ENCP_MACV_WAVE_END                         0x1bc6
#define ENCP_MACV_STRTLINE                         0x1bc7
#define ENCP_MACV_ENDLINE                          0x1bc8
#define ENCP_MACV_TS_CNT_MAX_L                     0x1bc9
#define ENCP_MACV_TS_CNT_MAX_H                     0x1bca
#define ENCP_MACV_TIME_DOWN                        0x1bcb
#define ENCP_MACV_TIME_LO                          0x1bcc
#define ENCP_MACV_TIME_UP                          0x1bcd
#define ENCP_MACV_TIME_RST                         0x1bce
#define ENCP_VBI_CTRL                              0x1bd0
#define ENCP_VBI_SETTING                           0x1bd1
#define ENCP_VBI_BEGIN                             0x1bd2
#define ENCP_VBI_WIDTH                             0x1bd3
#define ENCP_VBI_HVAL                              0x1bd4
#define ENCP_VBI_DATA0                             0x1bd5
#define ENCP_VBI_DATA1                             0x1bd6
#define C656_HS_ST                                 0x1be0
#define C656_HS_ED                                 0x1be1
#define C656_VS_LNST_E                             0x1be2
#define C656_VS_LNST_O                             0x1be3
#define C656_VS_LNED_E                             0x1be4
#define C656_VS_LNED_O                             0x1be5
#define C656_FS_LNST                               0x1be6
#define C656_FS_LNED                               0x1be7
#define ENCI_VIDEO_MODE                            0x1b00
#define ENCI_VIDEO_MODE_ADV                        0x1b01
#define ENCI_VIDEO_FSC_ADJ                         0x1b02
#define ENCI_VIDEO_BRIGHT                          0x1b03
#define ENCI_VIDEO_CONT                            0x1b04
#define ENCI_VIDEO_SAT                             0x1b05
#define ENCI_VIDEO_HUE                             0x1b06
#define ENCI_VIDEO_SCH                             0x1b07
#define ENCI_SYNC_MODE                             0x1b08
#define ENCI_SYNC_CTRL                             0x1b09
#define ENCI_SYNC_HSO_BEGIN                        0x1b0a
#define ENCI_SYNC_HSO_END                          0x1b0b
#define ENCI_SYNC_VSO_EVN                          0x1b0c
#define ENCI_SYNC_VSO_ODD                          0x1b0d
#define ENCI_SYNC_VSO_EVNLN                        0x1b0e
#define ENCI_SYNC_VSO_ODDLN                        0x1b0f
#define ENCI_SYNC_HOFFST                           0x1b10
#define ENCI_SYNC_VOFFST                           0x1b11
#define ENCI_SYNC_ADJ                              0x1b12
#define ENCI_RGB_SETTING                           0x1b13
#define ENCI_DE_H_BEGIN                            0x1b16
#define ENCI_DE_H_END                              0x1b17
#define ENCI_DE_V_BEGIN_EVEN                       0x1b18
#define ENCI_DE_V_END_EVEN                         0x1b19
#define ENCI_DE_V_BEGIN_ODD                        0x1b1a
#define ENCI_DE_V_END_ODD                          0x1b1b
#define ENCI_VBI_SETTING                           0x1b20
#define ENCI_VBI_CCDT_EVN                          0x1b21
#define ENCI_VBI_CCDT_ODD                          0x1b22
#define ENCI_VBI_CC525_LN                          0x1b23
#define ENCI_VBI_CC625_LN                          0x1b24
#define ENCI_VBI_WSSDT                             0x1b25
#define ENCI_VBI_WSS_LN                            0x1b26
#define ENCI_VBI_CGMSDT_L                          0x1b27
#define ENCI_VBI_CGMSDT_H                          0x1b28
#define ENCI_VBI_CGMS_LN                           0x1b29
#define ENCI_VBI_TTX_HTIME                         0x1b2a
#define ENCI_VBI_TTX_LN                            0x1b2b
#define ENCI_VBI_TTXDT0                            0x1b2c
#define ENCI_VBI_TTXDT1                            0x1b2d
#define ENCI_VBI_TTXDT2                            0x1b2e
#define ENCI_VBI_TTXDT3                            0x1b2f
#define ENCI_MACV_N0                               0x1b30
#define ENCI_MACV_N1                               0x1b31
#define ENCI_MACV_N2                               0x1b32
#define ENCI_MACV_N3                               0x1b33
#define ENCI_MACV_N4                               0x1b34
#define ENCI_MACV_N5                               0x1b35
#define ENCI_MACV_N6                               0x1b36
#define ENCI_MACV_N7                               0x1b37
#define ENCI_MACV_N8                               0x1b38
#define ENCI_MACV_N9                               0x1b39
#define ENCI_MACV_N10                              0x1b3a
#define ENCI_MACV_N11                              0x1b3b
#define ENCI_MACV_N12                              0x1b3c
#define ENCI_MACV_N13                              0x1b3d
#define ENCI_MACV_N14                              0x1b3e
#define ENCI_MACV_N15                              0x1b3f
#define ENCI_MACV_N16                              0x1b40
#define ENCI_MACV_N17                              0x1b41
#define ENCI_MACV_N18                              0x1b42
#define ENCI_MACV_N19                              0x1b43
#define ENCI_MACV_N20                              0x1b44
#define ENCI_MACV_N21                              0x1b45
#define ENCI_MACV_N22                              0x1b46
#define ENCI_DBG_PX_RST                            0x1b48
#define ENCI_DBG_FLDLN_RST                         0x1b49
#define ENCI_DBG_PX_INT                            0x1b4a
#define ENCI_DBG_FLDLN_INT                         0x1b4b
#define ENCI_DBG_MAXPX                             0x1b4c
#define ENCI_DBG_MAXLN                             0x1b4d
#define ENCI_MACV_MAX_AMP                          0x1b50
#define ENCI_MACV_PULSE_LO                         0x1b51
#define ENCI_MACV_PULSE_HI                         0x1b52
#define ENCI_MACV_BKP_MAX                          0x1b53
#define ENCI_CFILT_CTRL                            0x1b54
#define ENCI_CFILT7                                0x1b55
#define ENCI_YC_DELAY                              0x1b56
#define ENCI_VIDEO_EN                              0x1b57
#define ENCI_DVI_HSO_BEGIN                         0x1c00
#define ENCI_DVI_HSO_END                           0x1c01
#define ENCI_DVI_VSO_BLINE_EVN                     0x1c02
#define ENCI_DVI_VSO_BLINE_ODD                     0x1c03
#define ENCI_DVI_VSO_ELINE_EVN                     0x1c04
#define ENCI_DVI_VSO_ELINE_ODD                     0x1c05
#define ENCI_DVI_VSO_BEGIN_EVN                     0x1c06
#define ENCI_DVI_VSO_BEGIN_ODD                     0x1c07
#define ENCI_DVI_VSO_END_EVN                       0x1c08
#define ENCI_DVI_VSO_END_ODD                       0x1c09
#define ENCI_CFILT_CTRL2                           0x1c0a
#define ENCI_DACSEL_0                              0x1c0b
#define ENCI_DACSEL_1                              0x1c0c
#define ENCP_DACSEL_0                              0x1c0d
#define ENCP_DACSEL_1                              0x1c0e
#define ENCP_MAX_LINE_SWITCH_POINT                 0x1c0f
#define ENCI_TST_EN                                0x1c10
#define ENCI_TST_MDSEL                             0x1c11
#define ENCI_TST_Y                                 0x1c12
#define ENCI_TST_CB                                0x1c13
#define ENCI_TST_CR                                0x1c14
#define ENCI_TST_CLRBAR_STRT                       0x1c15
#define ENCI_TST_CLRBAR_WIDTH                      0x1c16
#define ENCI_TST_VDCNT_STSET                       0x1c17
#define ENCI_VFIFO2VD_CTL                          0x1c18
#define ENCI_VFIFO2VD_PIXEL_START                  0x1c19
#define ENCI_VFIFO2VD_PIXEL_END                    0x1c1a
#define ENCI_VFIFO2VD_LINE_TOP_START               0x1c1b
#define ENCI_VFIFO2VD_LINE_TOP_END                 0x1c1c
#define ENCI_VFIFO2VD_LINE_BOT_START               0x1c1d
#define ENCI_VFIFO2VD_LINE_BOT_END                 0x1c1e
#define ENCI_VFIFO2VD_CTL2                         0x1c1f
#define ENCT_VFIFO2VD_CTL                          0x1c20
#define ENCT_VFIFO2VD_PIXEL_START                  0x1c21
#define ENCT_VFIFO2VD_PIXEL_END                    0x1c22
#define ENCT_VFIFO2VD_LINE_TOP_START               0x1c23
#define ENCT_VFIFO2VD_LINE_TOP_END                 0x1c24
#define ENCT_VFIFO2VD_LINE_BOT_START               0x1c25
#define ENCT_VFIFO2VD_LINE_BOT_END                 0x1c26
#define ENCT_VFIFO2VD_CTL2                         0x1c27
#define ENCT_TST_EN                                0x1c28
#define ENCT_TST_MDSEL                             0x1c29
#define ENCT_TST_Y                                 0x1c2a
#define ENCT_TST_CB                                0x1c2b
#define ENCT_TST_CR                                0x1c2c
#define ENCT_TST_CLRBAR_STRT                       0x1c2d
#define ENCT_TST_CLRBAR_WIDTH                      0x1c2e
#define ENCT_TST_VDCNT_STSET                       0x1c2f
#define ENCP_DVI_HSO_BEGIN                         0x1c30
#define ENCP_DVI_HSO_END                           0x1c31
#define ENCP_DVI_VSO_BLINE_EVN                     0x1c32
#define ENCP_DVI_VSO_BLINE_ODD                     0x1c33
#define ENCP_DVI_VSO_ELINE_EVN                     0x1c34
#define ENCP_DVI_VSO_ELINE_ODD                     0x1c35
#define ENCP_DVI_VSO_BEGIN_EVN                     0x1c36
#define ENCP_DVI_VSO_BEGIN_ODD                     0x1c37
#define ENCP_DVI_VSO_END_EVN                       0x1c38
#define ENCP_DVI_VSO_END_ODD                       0x1c39
#define ENCP_DE_H_BEGIN                            0x1c3a
#define ENCP_DE_H_END                              0x1c3b
#define ENCP_DE_V_BEGIN_EVEN                       0x1c3c
#define ENCP_DE_V_END_EVEN                         0x1c3d
#define ENCP_DE_V_BEGIN_ODD                        0x1c3e
#define ENCP_DE_V_END_ODD                          0x1c3f
#define ENCI_SYNC_LINE_LENGTH                      0x1c40
#define ENCI_SYNC_PIXEL_EN                         0x1c41
#define ENCI_SYNC_TO_LINE_EN                       0x1c42
#define ENCI_SYNC_TO_PIXEL                         0x1c43
#define ENCP_SYNC_LINE_LENGTH                      0x1c44
#define ENCP_SYNC_PIXEL_EN                         0x1c45
#define ENCP_SYNC_TO_LINE_EN                       0x1c46
#define ENCP_SYNC_TO_PIXEL                         0x1c47
#define ENCT_SYNC_LINE_LENGTH                      0x1c48
#define ENCT_SYNC_PIXEL_EN                         0x1c49
#define ENCT_SYNC_TO_LINE_EN                       0x1c4a
#define ENCT_SYNC_TO_PIXEL                         0x1c4b
#define ENCL_SYNC_LINE_LENGTH                      0x1c4c
#define ENCL_SYNC_PIXEL_EN                         0x1c4d
#define ENCL_SYNC_TO_LINE_EN                       0x1c4e
#define ENCL_SYNC_TO_PIXEL                         0x1c4f
#define ENCP_VFIFO2VD_CTL2                         0x1c50
#define VENC_DVI_SETTING_MORE                      0x1c51
#define VENC_VDAC_DAC4_FILT_CTRL0                  0x1c54
#define VENC_VDAC_DAC4_FILT_CTRL1                  0x1c55
#define VENC_VDAC_DAC5_FILT_CTRL0                  0x1c56
#define VENC_VDAC_DAC5_FILT_CTRL1                  0x1c57
#define VENC_VDAC_DAC0_FILT_CTRL0                  0x1c58
#define VENC_VDAC_DAC0_FILT_CTRL1                  0x1c59
#define VENC_VDAC_DAC1_FILT_CTRL0                  0x1c5a
#define VENC_VDAC_DAC1_FILT_CTRL1                  0x1c5b
#define VENC_VDAC_DAC2_FILT_CTRL0                  0x1c5c
#define VENC_VDAC_DAC2_FILT_CTRL1                  0x1c5d
#define VENC_VDAC_DAC3_FILT_CTRL0                  0x1c5e
#define VENC_VDAC_DAC3_FILT_CTRL1                  0x1c5f
#define ENCT_VIDEO_EN                              0x1c60
#define ENCT_VIDEO_Y_SCL                           0x1c61
#define ENCT_VIDEO_PB_SCL                          0x1c62
#define ENCT_VIDEO_PR_SCL                          0x1c63
#define ENCT_VIDEO_Y_OFFST                         0x1c64
#define ENCT_VIDEO_PB_OFFST                        0x1c65
#define ENCT_VIDEO_PR_OFFST                        0x1c66
#define ENCT_VIDEO_MODE                            0x1c67
#define ENCT_VIDEO_MODE_ADV                        0x1c68
#define ENCT_DBG_PX_RST                            0x1c69
#define ENCT_DBG_LN_RST                            0x1c6a
#define ENCT_DBG_PX_INT                            0x1c6b
#define ENCT_DBG_LN_INT                            0x1c6c
#define ENCT_VIDEO_YFP1_HTIME                      0x1c6d
#define ENCT_VIDEO_YFP2_HTIME                      0x1c6e
#define ENCT_VIDEO_YC_DLY                          0x1c6f
#define ENCT_VIDEO_MAX_PXCNT                       0x1c70
#define ENCT_VIDEO_HAVON_END                       0x1c71
#define ENCT_VIDEO_HAVON_BEGIN                     0x1c72
#define ENCT_VIDEO_VAVON_ELINE                     0x1c73
#define ENCT_VIDEO_VAVON_BLINE                     0x1c74
#define ENCT_VIDEO_HSO_BEGIN                       0x1c75
#define ENCT_VIDEO_HSO_END                         0x1c76
#define ENCT_VIDEO_VSO_BEGIN                       0x1c77
#define ENCT_VIDEO_VSO_END                         0x1c78
#define ENCT_VIDEO_VSO_BLINE                       0x1c79
#define ENCT_VIDEO_VSO_ELINE                       0x1c7a
#define ENCT_VIDEO_MAX_LNCNT                       0x1c7b
#define ENCT_VIDEO_BLANKY_VAL                      0x1c7c
#define ENCT_VIDEO_BLANKPB_VAL                     0x1c7d
#define ENCT_VIDEO_BLANKPR_VAL                     0x1c7e
#define ENCT_VIDEO_HOFFST                          0x1c7f
#define ENCT_VIDEO_VOFFST                          0x1c80
#define ENCT_VIDEO_RGB_CTRL                        0x1c81
#define ENCT_VIDEO_FILT_CTRL                       0x1c82
#define ENCT_VIDEO_OFLD_VPEQ_OFST                  0x1c83
#define ENCT_VIDEO_OFLD_VOAV_OFST                  0x1c84
#define ENCT_VIDEO_MATRIX_CB                       0x1c85
#define ENCT_VIDEO_MATRIX_CR                       0x1c86
#define ENCT_VIDEO_RGBIN_CTRL                      0x1c87
#define ENCT_MAX_LINE_SWITCH_POINT                 0x1c88
#define ENCT_DACSEL_0                              0x1c89
#define ENCT_DACSEL_1                              0x1c8a
#define ENCL_VFIFO2VD_CTL                          0x1c90
#define ENCL_VFIFO2VD_PIXEL_START                  0x1c91
#define ENCL_VFIFO2VD_PIXEL_END                    0x1c92
#define ENCL_VFIFO2VD_LINE_TOP_START               0x1c93
#define ENCL_VFIFO2VD_LINE_TOP_END                 0x1c94
#define ENCL_VFIFO2VD_LINE_BOT_START               0x1c95
#define ENCL_VFIFO2VD_LINE_BOT_END                 0x1c96
#define ENCL_VFIFO2VD_CTL2                         0x1c97
#define ENCL_TST_EN                                0x1c98
#define ENCL_TST_MDSEL                             0x1c99
#define ENCL_TST_Y                                 0x1c9a
#define ENCL_TST_CB                                0x1c9b
#define ENCL_TST_CR                                0x1c9c
#define ENCL_TST_CLRBAR_STRT                       0x1c9d
#define ENCL_TST_CLRBAR_WIDTH                      0x1c9e
#define ENCL_TST_VDCNT_STSET                       0x1c9f
#define ENCL_VIDEO_EN                              0x1ca0
#define ENCL_VIDEO_Y_SCL                           0x1ca1
#define ENCL_VIDEO_PB_SCL                          0x1ca2
#define ENCL_VIDEO_PR_SCL                          0x1ca3
#define ENCL_VIDEO_Y_OFFST                         0x1ca4
#define ENCL_VIDEO_PB_OFFST                        0x1ca5
#define ENCL_VIDEO_PR_OFFST                        0x1ca6
#define ENCL_VIDEO_MODE                            0x1ca7
#define ENCL_VIDEO_MODE_ADV                        0x1ca8
#define ENCL_DBG_PX_RST                            0x1ca9
#define ENCL_DBG_LN_RST                            0x1caa
#define ENCL_DBG_PX_INT                            0x1cab
#define ENCL_DBG_LN_INT                            0x1cac
#define ENCL_VIDEO_YFP1_HTIME                      0x1cad
#define ENCL_VIDEO_YFP2_HTIME                      0x1cae
#define ENCL_VIDEO_YC_DLY                          0x1caf
#define ENCL_VIDEO_MAX_PXCNT                       0x1cb0
#define ENCL_VIDEO_HAVON_END                       0x1cb1
#define ENCL_VIDEO_HAVON_BEGIN                     0x1cb2
#define ENCL_VIDEO_VAVON_ELINE                     0x1cb3
#define ENCL_VIDEO_VAVON_BLINE                     0x1cb4
#define ENCL_VIDEO_HSO_BEGIN                       0x1cb5
#define ENCL_VIDEO_HSO_END                         0x1cb6
#define ENCL_VIDEO_VSO_BEGIN                       0x1cb7
#define ENCL_VIDEO_VSO_END                         0x1cb8
#define ENCL_VIDEO_VSO_BLINE                       0x1cb9
#define ENCL_VIDEO_VSO_ELINE                       0x1cba
#define ENCL_VIDEO_MAX_LNCNT                       0x1cbb
#define ENCL_VIDEO_BLANKY_VAL                      0x1cbc
#define ENCL_VIDEO_BLANKPB_VAL                     0x1cbd
#define ENCL_VIDEO_BLANKPR_VAL                     0x1cbe
#define ENCL_VIDEO_HOFFST                          0x1cbf
#define ENCL_VIDEO_VOFFST                          0x1cc0
#define ENCL_VIDEO_RGB_CTRL                        0x1cc1
#define ENCL_VIDEO_FILT_CTRL                       0x1cc2
#define ENCL_VIDEO_OFLD_VPEQ_OFST                  0x1cc3
#define ENCL_VIDEO_OFLD_VOAV_OFST                  0x1cc4
#define ENCL_VIDEO_MATRIX_CB                       0x1cc5
#define ENCL_VIDEO_MATRIX_CR                       0x1cc6
#define ENCL_VIDEO_RGBIN_CTRL                      0x1cc7
#define ENCL_MAX_LINE_SWITCH_POINT                 0x1cc8
#define ENCL_DACSEL_0                              0x1cc9
#define ENCL_DACSEL_1                              0x1cca
#define RDMA_AHB_START_ADDR_MAN                    0x1cf0
#define RDMA_AHB_END_ADDR_MAN                      0x1cf1
#define RDMA_AHB_START_ADDR_1                      0x1cf2
#define RDMA_AHB_END_ADDR_1                        0x1cf3
#define RDMA_AHB_START_ADDR_2                      0x1cf4
#define RDMA_AHB_END_ADDR_2                        0x1cf5
#define RDMA_AHB_START_ADDR_3                      0x1cf6
#define RDMA_AHB_END_ADDR_3                        0x1cf7
#define RDMA_ACCESS_AUTO                           0x1cf8
#define RDMA_ACCESS_MAN                            0x1cf9
#define RDMA_CTRL                                  0x1cfa
#define RDMA_STATUS                                0x1cfb
#define L_GAMMA_CNTL_PORT                          0x1400
#define L_GAMMA_DATA_PORT                          0x1401
#define L_GAMMA_ADDR_PORT                          0x1402
#define L_GAMMA_VCOM_HSWITCH_ADDR                  0x1403
#define L_RGB_BASE_ADDR                            0x1405
#define L_RGB_COEFF_ADDR                           0x1406
#define L_POL_CNTL_ADDR                            0x1407
#define L_DITH_CNTL_ADDR                           0x1408
#define L_STH1_HS_ADDR                             0x1410
#define L_STH1_HE_ADDR                             0x1411
#define L_STH1_VS_ADDR                             0x1412
#define L_STH1_VE_ADDR                             0x1413
#define L_STH2_HS_ADDR                             0x1414
#define L_STH2_HE_ADDR                             0x1415
#define L_STH2_VS_ADDR                             0x1416
#define L_STH2_VE_ADDR                             0x1417
#define L_OEH_HS_ADDR                              0x1418
#define L_OEH_HE_ADDR                              0x1419
#define L_OEH_VS_ADDR                              0x141a
#define L_OEH_VE_ADDR                              0x141b
#define L_VCOM_HSWITCH_ADDR                        0x141c
#define L_VCOM_VS_ADDR                             0x141d
#define L_VCOM_VE_ADDR                             0x141e
#define L_CPV1_HS_ADDR                             0x141f
#define L_CPV1_HE_ADDR                             0x1420
#define L_CPV1_VS_ADDR                             0x1421
#define L_CPV1_VE_ADDR                             0x1422
#define L_CPV2_HS_ADDR                             0x1423
#define L_CPV2_HE_ADDR                             0x1424
#define L_CPV2_VS_ADDR                             0x1425
#define L_CPV2_VE_ADDR                             0x1426
#define L_STV1_HS_ADDR                             0x1427
#define L_STV1_HE_ADDR                             0x1428
#define L_STV1_VS_ADDR                             0x1429
#define L_STV1_VE_ADDR                             0x142a
#define L_STV2_HS_ADDR                             0x142b
#define L_STV2_HE_ADDR                             0x142c
#define L_STV2_VS_ADDR                             0x142d
#define L_STV2_VE_ADDR                             0x142e
#define L_OEV1_HS_ADDR                             0x142f
#define L_OEV1_HE_ADDR                             0x1430
#define L_OEV1_VS_ADDR                             0x1431
#define L_OEV1_VE_ADDR                             0x1432
#define L_OEV2_HS_ADDR                             0x1433
#define L_OEV2_HE_ADDR                             0x1434
#define L_OEV2_VS_ADDR                             0x1435
#define L_OEV2_VE_ADDR                             0x1436
#define L_OEV3_HS_ADDR                             0x1437
#define L_OEV3_HE_ADDR                             0x1438
#define L_OEV3_VS_ADDR                             0x1439
#define L_OEV3_VE_ADDR                             0x143a
#define L_LCD_PWR_ADDR                             0x143b
#define L_LCD_PWM0_LO_ADDR                         0x143c
#define L_LCD_PWM0_HI_ADDR                         0x143d
#define L_LCD_PWM1_LO_ADDR                         0x143e
#define L_LCD_PWM1_HI_ADDR                         0x143f
#define L_INV_CNT_ADDR                             0x1440
#define L_TCON_MISC_SEL_ADDR                       0x1441
#define L_DUAL_PORT_CNTL_ADDR                      0x1442
#define L_TCON_DOUBLE_CTL                          0x1449
#define L_TCON_PATTERN_HI                          0x144a
#define L_TCON_PATTERN_LO                          0x144b
#define L_DE_HS_ADDR                               0x1451
#define L_DE_HE_ADDR                               0x1452
#define L_DE_VS_ADDR                               0x1453
#define L_DE_VE_ADDR                               0x1454
#define L_HSYNC_HS_ADDR                            0x1455
#define L_HSYNC_HE_ADDR                            0x1456
#define L_HSYNC_VS_ADDR                            0x1457
#define L_HSYNC_VE_ADDR                            0x1458
#define L_VSYNC_HS_ADDR                            0x1459
#define L_VSYNC_HE_ADDR                            0x145a
#define L_VSYNC_VS_ADDR                            0x145b
#define L_VSYNC_VE_ADDR                            0x145c
#define L_LCD_MCU_CTL                              0x145d
#define GAMMA_CNTL_PORT                            0x1480
#define GAMMA_DATA_PORT                            0x1481
#define GAMMA_ADDR_PORT                            0x1482
#define GAMMA_VCOM_HSWITCH_ADDR                    0x1483
#define RGB_BASE_ADDR                              0x1485
#define RGB_COEFF_ADDR                             0x1486
#define POL_CNTL_ADDR                              0x1487
#define DITH_CNTL_ADDR                             0x1488
#define STH1_HS_ADDR                               0x1490
#define STH1_HE_ADDR                               0x1491
#define STH1_VS_ADDR                               0x1492
#define STH1_VE_ADDR                               0x1493
#define STH2_HS_ADDR                               0x1494
#define STH2_HE_ADDR                               0x1495
#define STH2_VS_ADDR                               0x1496
#define STH2_VE_ADDR                               0x1497
#define OEH_HS_ADDR                                0x1498
#define OEH_HE_ADDR                                0x1499
#define OEH_VS_ADDR                                0x149a
#define OEH_VE_ADDR                                0x149b
#define VCOM_HSWITCH_ADDR                          0x149c
#define VCOM_VS_ADDR                               0x149d
#define VCOM_VE_ADDR                               0x149e
#define CPV1_HS_ADDR                               0x149f
#define CPV1_HE_ADDR                               0x14a0
#define CPV1_VS_ADDR                               0x14a1
#define CPV1_VE_ADDR                               0x14a2
#define CPV2_HS_ADDR                               0x14a3
#define CPV2_HE_ADDR                               0x14a4
#define CPV2_VS_ADDR                               0x14a5
#define CPV2_VE_ADDR                               0x14a6
#define STV1_HS_ADDR                               0x14a7
#define STV1_HE_ADDR                               0x14a8
#define STV1_VS_ADDR                               0x14a9
#define STV1_VE_ADDR                               0x14aa
#define STV2_HS_ADDR                               0x14ab
#define STV2_HE_ADDR                               0x14ac
#define STV2_VS_ADDR                               0x14ad
#define STV2_VE_ADDR                               0x14ae
#define OEV1_HS_ADDR                               0x14af
#define OEV1_HE_ADDR                               0x14b0
#define OEV1_VS_ADDR                               0x14b1
#define OEV1_VE_ADDR                               0x14b2
#define OEV2_HS_ADDR                               0x14b3
#define OEV2_HE_ADDR                               0x14b4
#define OEV2_VS_ADDR                               0x14b5
#define OEV2_VE_ADDR                               0x14b6
#define OEV3_HS_ADDR                               0x14b7
#define OEV3_HE_ADDR                               0x14b8
#define OEV3_VS_ADDR                               0x14b9
#define OEV3_VE_ADDR                               0x14ba
#define LCD_PWR_ADDR                               0x14bb
#define LCD_PWM0_LO_ADDR                           0x14bc
#define LCD_PWM0_HI_ADDR                           0x14bd
#define LCD_PWM1_LO_ADDR                           0x14be
#define LCD_PWM1_HI_ADDR                           0x14bf
#define INV_CNT_ADDR                               0x14c0
#define TCON_MISC_SEL_ADDR                         0x14c1
#define DUAL_PORT_CNTL_ADDR                        0x14c2
#define MLVDS_CONTROL                              0x14c3
#define MLVDS_RESET_PATTERN_HI                     0x14c4
#define MLVDS_RESET_PATTERN_LO                     0x14c5
#define MLVDS_RESET_PATTERN_EXT                    0x14c6
#define MLVDS_CONFIG_HI                            0x14c7
#define MLVDS_CONFIG_LO                            0x14c8
#define TCON_DOUBLE_CTL                            0x14c9
#define TCON_PATTERN_HI                            0x14ca
#define TCON_PATTERN_LO                            0x14cb
#define TCON_CONTROL_HI                            0x14cc
#define TCON_CONTROL_LO                            0x14cd
#define LVDS_BLANK_DATA_HI                         0x14ce
#define LVDS_BLANK_DATA_LO                         0x14cf
#define LVDS_PACK_CNTL_ADDR                        0x14d0
#define DE_HS_ADDR                                 0x14d1
#define DE_HE_ADDR                                 0x14d2
#define DE_VS_ADDR                                 0x14d3
#define DE_VE_ADDR                                 0x14d4
#define HSYNC_HS_ADDR                              0x14d5
#define HSYNC_HE_ADDR                              0x14d6
#define HSYNC_VS_ADDR                              0x14d7
#define HSYNC_VE_ADDR                              0x14d8
#define VSYNC_HS_ADDR                              0x14d9
#define VSYNC_HE_ADDR                              0x14da
#define VSYNC_VS_ADDR                              0x14db
#define VSYNC_VE_ADDR                              0x14dc
#define LCD_MCU_CTL                                0x14dd
#define LCD_MCU_DATA_0                             0x14de
#define LCD_MCU_DATA_1                             0x14df
#define LVDS_GEN_CNTL                              0x14e0
#define LVDS_PHY_CNTL0                             0x14e1
#define LVDS_PHY_CNTL1                             0x14e2
#define LVDS_PHY_CNTL2                             0x14e3
#define LVDS_PHY_CNTL3                             0x14e4
#define LVDS_PHY_CNTL4                             0x14e5
#define LVDS_PHY_CNTL5                             0x14e6
#define LVDS_SRG_TEST                              0x14e8
#define LVDS_BIST_MUX0                             0x14e9
#define LVDS_BIST_MUX1                             0x14ea
#define LVDS_BIST_FIXED0                           0x14eb
#define LVDS_BIST_FIXED1                           0x14ec
#define LVDS_BIST_CNTL0                            0x14ed
#define LVDS_CLKB_CLKA                             0x14ee
#define LVDS_PHY_CLK_CNTL                          0x14ef
#define LVDS_SER_EN                                0x14f0
#define LVDS_PHY_CNTL6                             0x14f1
#define LVDS_PHY_CNTL7                             0x14f2
#define LVDS_PHY_CNTL8                             0x14f3
#define MLVDS_CLK_CTL_HI                           0x14f4
#define MLVDS_CLK_CTL_LO                           0x14f5
#define MLVDS_DUAL_GATE_WR_START                   0x14f6
#define MLVDS_DUAL_GATE_WR_END                     0x14f7
#define MLVDS_DUAL_GATE_RD_START                   0x14f8
#define MLVDS_DUAL_GATE_RD_END                     0x14f9
#define MLVDS_SECOND_RESET_CTL                     0x14fa
#define MLVDS_DUAL_GATE_CTL_HI                     0x14fb
#define MLVDS_DUAL_GATE_CTL_LO                     0x14fc
#define MLVDS_RESET_CONFIG_HI                      0x14fd
#define MLVDS_RESET_CONFIG_LO                      0x14fe
#define VPU_OSD1_MMC_CTRL                          0x2701
#define VPU_OSD2_MMC_CTRL                          0x2702
#define VPU_VD1_MMC_CTRL                           0x2703
#define VPU_VD2_MMC_CTRL                           0x2704
#define VPU_DI_IF1_MMC_CTRL                        0x2705
#define VPU_DI_MEM_MMC_CTRL                        0x2706
#define VPU_DI_INP_MMC_CTRL                        0x2707
#define VPU_DI_MTNRD_MMC_CTRL                      0x2708
#define VPU_DI_CHAN2_MMC_CTRL                      0x2709
#define VPU_DI_MTNWR_MMC_CTRL                      0x270a
#define VPU_DI_NRWR_MMC_CTRL                       0x270b
#define VPU_DI_DIWR_MMC_CTRL                       0x270c
#define VPU_VDIN0_MMC_CTRL                         0x270d
#define VPU_VDIN1_MMC_CTRL                         0x270e
#define VPU_BT656_MMC_CTRL                         0x270f
#define VPU_TVD3D_MMC_CTRL                         0x2710
#define VPU_TVDVBI_MMC_CTRL                        0x2711
#define VPU_TVDVBI_VSLATCH_ADDR                    0x2712
#define VPU_TVDVBI_WRRSP_ADDR                      0x2713
#define VPU_VDIN_PRE_ARB_CTRL                      0x2714
#define VPU_VDISP_PRE_ARB_CTRL                     0x2715
#define VPU_VPUARB2_PRE_ARB_CTRL                   0x2716
#define VPU_OSD3_MMC_CTRL                          0x2717
#define VPU_OSD4_MMC_CTRL                          0x2718
#define VPU_VD3_MMC_CTRL                           0x2719
#define VPU_VIU_VENC_MUX_CTRL                      0x271a
#define VPU_HDMI_SETTING                           0x271b
#define ENCI_INFO_READ                             0x271c
#define ENCP_INFO_READ                             0x271d
#define ENCT_INFO_READ                             0x271e
#define ENCL_INFO_READ                             0x271f
#define AUDIO_COP_CTL2                             0x2f01
#define OPERAND_M_CTL                              0x2f02
#define OPERAND1_ADDR                              0x2f03
#define OPERAND2_ADDR                              0x2f04
#define RESULT_M_CTL                               0x2f05
#define RESULT1_ADDR                               0x2f06
#define RESULT2_ADDR                               0x2f07
#define ADD_SHFT_CTL                               0x2f08
#define OPERAND_ONE_H                              0x2f09
#define OPERAND_ONE_L                              0x2f0a
#define OPERAND_TWO_H                              0x2f0b
#define OPERAND_TWO_L                              0x2f0c
#define RESULT_H                                   0x2f0d
#define RESULT_M                                   0x2f0e
#define RESULT_L                                   0x2f0f
#define WMEM_R_PTR                                 0x2f10
#define WMEM_W_PTR                                 0x2f11
#define AUDIO_LAYER                                0x2f20
#define AC3_DECODING                               0x2f21
#define AC3_DYNAMIC                                0x2f22
#define AC3_MELODY                                 0x2f23
#define AC3_VOCAL                                  0x2f24
#define ASSIST_AMR_SCRATCH0                        0x1f4f
#define ASSIST_AMR_SCRATCH1                        0x1f50
#define ASSIST_AMR_SCRATCH2                        0x1f51
#define ASSIST_AMR_SCRATCH3                        0x1f52
#define ASSIST_HW_REV                              0x1f53
#define ASSIST_POR_CONFIG                          0x1f55
#define ASSIST_SPARE16_REG1                        0x1f56
#define ASSIST_SPARE16_REG2                        0x1f57
#define ASSIST_SPARE8_REG1                         0x1f58
#define ASSIST_SPARE8_REG2                         0x1f59
#define ASSIST_SPARE8_REG3                         0x1f5a
#define AC3_CTRL_REG1                              0x1f5b
#define AC3_CTRL_REG2                              0x1f5c
#define AC3_CTRL_REG3                              0x1f5d
#define AC3_CTRL_REG4                              0x1f5e
#define ASSIST_GEN_CNTL                            0x1f68
#define AUDIN_SPDIF_MODE                           0x2800
#define AUDIN_SPDIF_FS_CLK_RLTN                    0x2801
#define AUDIN_SPDIF_CHNL_STS_A                     0x2802
#define AUDIN_SPDIF_CHNL_STS_B                     0x2803
#define AUDIN_SPDIF_MISC                           0x2804
#define AUDIN_SPDIF_NPCM_PCPD                      0x2805
#define AUDIN_SPDIF_END                            0x280f
#define AUDIN_I2SIN_CTRL                           0x2810
#define AUDIN_SOURCE_SEL                           0x2811
#define AUDIN_FIFO0_START                          0x2820
#define AUDIN_FIFO0_END                            0x2821
#define AUDIN_FIFO0_PTR                            0x2822
#define AUDIN_FIFO0_INTR                           0x2823
#define AUDIN_FIFO0_RDPTR                          0x2824
#define AUDIN_FIFO0_CTRL                           0x2825
#define AUDIN_FIFO0_CTRL1                          0x2826
#define AUDIN_FIFO0_LVL0                           0x2827
#define AUDIN_FIFO0_LVL1                           0x2828
#define AUDIN_FIFO0_LVL2                           0x2829
#define AUDIN_FIFO1_START                          0x282a
#define AUDIN_FIFO1_END                            0x282b
#define AUDIN_FIFO1_PTR                            0x282c
#define AUDIN_FIFO1_INTR                           0x282d
#define AUDIN_FIFO1_RDPTR                          0x282e
#define AUDIN_FIFO1_CTRL                           0x282f
#define AUDIN_FIFO1_CTRL1                          0x2830
#define AUDIN_FIFO1_LVL0                           0x2831
#define AUDIN_FIFO1_LVL1                           0x2832
#define AUDIN_FIFO1_LVL2                           0x2833
#define AUDIN_FIFO0_REQID                          0x2834
#define AUDIN_FIFO1_REQID                          0x2835
#define AUDIN_INT_CTRL                             0x2836
#define AUDIN_FIFO_INT                             0x2837
#define AUDIN_FIFO0_WRAP                           0x2838
#define AUDIN_FIFO1_WRAP                           0x2839
#define AUDIN_PIO_STS                              0x283a
#define AUDIN_RD_L                                 0x283b
#define AUDIN_RD_H                                 0x283c
#define PCMIN_CTRL0                                0x2840
#define PCMIN_CTRL1                                0x2841
#define PCMOUT_CTRL0                               0x2850
#define PCMOUT_CTRL1                               0x2851
#define PCMOUT_CTRL2                               0x2852
#define PCMOUT_CTRL3                               0x2853
#define AUDOUT_CTRL                                0x2860
#define AUDOUT_CTRL1                               0x2861
#define AUDOUT_BUF0_STA                            0x2862
#define AUDOUT_BUF0_EDA                            0x2863
#define AUDOUT_BUF0_WPTR                           0x2864
#define AUDOUT_BUF1_STA                            0x2865
#define AUDOUT_BUF1_EDA                            0x2866
#define AUDOUT_BUF1_WPTR                           0x2867
#define AUDOUT_FIFO_RPTR                           0x2868
#define AUDOUT_INTR_PTR                            0x2869
#define AUDOUT_FIFO_STS                            0x286a
#define AUDOUT_WR_L                                0x286b
#define AUDOUT_WR_H                                0x286c
#define AUDIN_ADDR_END                             0x287f
